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1. 发明申请

US20120292669A1 FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME 有权
标题翻译：场效应晶体管结构及其形成方法
公开(公告)号：US20120292669A1
公开(公告)日：2012-11-22
申请号：US13108305
申请日：2011-05-16
申请人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
摘要翻译：本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

2. 发明授权

US08618583B2 Junction gate field effect transistor structure having n-channel 有权
标题翻译：具有n沟道的结栅场效应晶体管结构
公开(公告)号：US08618583B2
公开(公告)日：2013-12-31
申请号：US13108305
申请日：2011-05-16
申请人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： Panglijen Candra , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/66 , H01L21/70 , H01L21/337
CPC分类号： H01L29/808 , H01L29/0649 , H01L29/1075 , H01L29/66901
摘要： The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region.
摘要翻译：本公开总体上涉及结栅场效应晶体管（JFET）结构及其形成方法。 JFET结构包括其中具有p区的p型衬底; 一条n通道; 在n沟道内的n掺杂的增强区域，每个n掺杂的增强区域与p区域分离。

3. 发明授权

US07670889B2 Structure and method for fabrication JFET in CMOS 失效
标题翻译： CMOS中制造JFET的结构和方法
公开(公告)号：US07670889B2
公开(公告)日：2010-03-02
申请号：US12132638
申请日：2008-06-04
申请人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/337 , H01L21/84
CPC分类号： H01L29/8086 , H01L29/66901
摘要： A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.
摘要翻译：更具体地，涉及用于制造SOI中的JFET的设计结构，JFET和制造JFET的方法。 JFET包括直接在SOI层上形成的栅极多晶硅，并且栅极氧化层插入在栅极多晶硅和SOI层的外边缘之间。

4. 发明申请

US20090302355A1 STRUCTURE, STRUCTURE AND METHOD FOR FABRICATION JFET IN CMOS 失效
标题翻译： CMOS中的制造JFET的结构，结构和方法
公开(公告)号：US20090302355A1
公开(公告)日：2009-12-10
申请号：US12132638
申请日：2008-06-04
申请人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
发明人： John J. Pekarik , Richard A. Phelps , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/808 , H01L21/337 , G06F17/50
CPC分类号： H01L29/8086 , H01L29/66901
摘要： A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.
摘要翻译：更具体地，涉及用于制造SOI中的JFET的设计结构，JFET和制造JFET的方法。 JFET包括直接在SOI层上形成的栅极多晶硅，并且栅极氧化层插入在栅极多晶硅和SOI层的外边缘之间。

5. 发明授权

US09041105B2 Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
标题翻译：集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构
公开(公告)号：US09041105B2
公开(公告)日：2015-05-26
申请号：US13553947
申请日：2012-07-20
申请人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
发明人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/088 , H01L27/12 , H01L21/84 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/84
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

6. 发明申请

US20100248432A1 METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT 有权
标题翻译：形成用于集成电路的高压P-N结和设计结构的方法
公开(公告)号：US20100248432A1
公开(公告)日：2010-09-30
申请号：US12795108
申请日：2010-06-07
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L21/84 , G06F17/50
CPC分类号： H01L29/93
摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.
摘要翻译：形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

7. 发明授权

US07804119B2 Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit 失效
标题翻译：具有超陡P-N结的器件结构，形成超陡P-N结的方法，以及集成电路的设计结构
公开(公告)号：US07804119B2
公开(公告)日：2010-09-28
申请号：US12099316
申请日：2008-04-08
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/108
CPC分类号： H01L29/93
摘要： Device structures with hyper-abrupt p-n junctions, methods of forming hyper-abrupt p-n junctions, and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt-n junction.
摘要翻译：具有超突变p-n结的器件结构，形成超突变p-n结的方法以及包含具有超突变p-n结的器件结构的集成电路的设计结构。通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。反渗透定义了超突变p-n结。在离子注入期间，在器件层的顶表面上承载的栅极结构作为硬掩模进行操作，以有助于限定超突变n结的横向边界。

8. 发明授权

US08518782B2 Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure 有权
标题翻译：半导体器件包括非对称轻掺杂漏极（LDD）区域，相关方法和设计结构
公开(公告)号：US08518782B2
公开(公告)日：2013-08-27
申请号：US12963054
申请日：2010-12-08
申请人： Alan B. Botula , Robert M. Rassel , Yun Shi , Mark E. Stidham
发明人： Alan B. Botula , Robert M. Rassel , Yun Shi , Mark E. Stidham
IPC分类号： H01L21/426
CPC分类号： H01L29/7833 , H01L21/26586 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.
摘要翻译：公开了一种半导体器件。半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。还公开了相关的方法和设计结构。

9. 发明申请

US20120199907A1 LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE 有权
标题翻译： SOI衬底中的横向高压连接变压器二极管
公开(公告)号：US20120199907A1
公开(公告)日：2012-08-09
申请号：US13449419
申请日：2012-04-18
申请人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
发明人： Jeffrey B. Johnson , Alvin J. Joseph , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/12 , G06F17/50
CPC分类号： H01L29/93 , H01L29/7391
摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.
摘要翻译：变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。在第二掺杂半导体区域和第二电极之间形成超破坏结。栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。还提供了变容二极管的设计结构。

10. 发明申请

US20110284961A1 SELF-ALIGNED SCHOTTKY DIODE 有权
标题翻译：自对准肖特基二极管
公开(公告)号：US20110284961A1
公开(公告)日：2011-11-24
申请号：US13197414
申请日：2011-08-03
申请人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
发明人： Alan B. Botula , Alvin J. Joseph , Alan F. Norris , Robert M. Rassel , Yun Shi
IPC分类号： H01L29/786 , G06F17/50 , G06F11/22
CPC分类号： H01L29/7839 , H01L21/26586 , H01L29/665 , H01L29/66643 , H01L29/66659
摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.
摘要翻译：肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构另一侧的掺杂保护环。肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。还提供了用于本发明的肖特基势垒二极管的设计结构。

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