专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080242117A1 APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS 审中-公开
标题翻译：减少波浪边缘温度和破裂的设备
公开(公告)号：US20080242117A1
公开(公告)日：2008-10-02
申请号：US11694934
申请日：2007-03-30
申请人： Panchapakesan Ramanarayanan , Karson Knutson , Jack Hwang , John Leonard , Sridhar Govindaraju
发明人： Panchapakesan Ramanarayanan , Karson Knutson , Jack Hwang , John Leonard , Sridhar Govindaraju
IPC分类号： H01L21/324
CPC分类号： H01L21/324 , H01L21/67115
摘要： In some embodiments radiation incident on a wafer is provided to perform an annealing process, and the wafer is cooled at an edge portion to reduce temperature and stress on the wafer. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，提供入射在晶片上的辐射以执行退火处理，并且晶片在边缘部分被冷却以降低晶片上的温度和应力。描述和要求保护其他实施例。

2. 发明申请

US20090323759A1 Temperature measurement with reduced extraneous infrared in a processing chamber 失效
标题翻译：在处理室内减少外来红外线的温度测量
公开(公告)号：US20090323759A1
公开(公告)日：2009-12-31
申请号：US12217063
申请日：2008-06-30
申请人： Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli , Jack Hwang
发明人： Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli , Jack Hwang
IPC分类号： G01J5/06 , H05B6/00
CPC分类号： H05B6/645 , G01J5/0003 , G01J5/0007 , G01J5/08 , G01J5/0806 , G01J5/0862
摘要： Temperature measurement using a pyrometer in a processing chamber is described. The extraneous light received by the pyrometer is reduced. In one example, a photodetector is used to measure the intensity of light within the processing chamber at a defined wavelength. A temperature circuit is used to convert the measured light intensity to a temperature signal, and a doped optical window between a heat source and a workpiece inside processing chamber is used to absorb light at the defined wavelength directed at the workpiece from the heat source.
摘要翻译：描述了在处理室中使用高温计的温度测量。高温计所接收的外部光线减少。在一个示例中，光电检测器用于以规定的波长测量处理室内的光的强度。使用温度电路将测量的光强度转换为温度信号，并且在处理室内的热源和工件之间的掺杂光学窗口用于从热源吸收指向工件的限定波长的光。

3. 发明授权

US07758238B2 Temperature measurement with reduced extraneous infrared in a processing chamber 失效
标题翻译：在处理室内减少外来红外线的温度测量
公开(公告)号：US07758238B2
公开(公告)日：2010-07-20
申请号：US12217063
申请日：2008-06-30
申请人： Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli , Jack Hwang
发明人： Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli , Jack Hwang
IPC分类号： G01K5/00 , G01K13/00 , G01J5/00
CPC分类号： H05B6/645 , G01J5/0003 , G01J5/0007 , G01J5/08 , G01J5/0806 , G01J5/0862
摘要： Temperature measurement using a pyrometer in a processing chamber is described. The extraneous light received by the pyrometer is reduced. In one example, a photodetector is used to measure the intensity of light within the processing chamber at a defined wavelength. A temperature circuit is used to convert the measured light intensity to a temperature signal, and a doped optical window between a heat source and a workpiece inside processing chamber is used to absorb light at the defined wavelength directed at the workpiece from the heat source.
摘要翻译：描述了在处理室中使用高温计的温度测量。高温计所接收的外部光线减少。在一个示例中，光电检测器用于以规定的波长测量处理室内的光的强度。使用温度电路将测量的光强度转换为温度信号，并且在处理室内的热源和工件之间的掺杂光学窗口用于从热源吸收指向工件的限定波长的光。

4. 发明申请

US20090325392A1 SUB-SECOND ANNEALING PROCESSES FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的次二次退火工艺
公开(公告)号：US20090325392A1
公开(公告)日：2009-12-31
申请号：US12164560
申请日：2008-06-30
申请人： Jack Hwang , Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli
发明人： Jack Hwang , Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli
IPC分类号： H01L21/26
CPC分类号： H01L21/324 , H01L21/28518 , H01L29/665
摘要： An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.
摘要翻译：描述用于半导体制造的退火方法和装置。该方法和装置允许可以跨越热预算的退火，并且可以针对具体过程及其对应的激活能量进行定制。在一些情况下，退火方法跨越约1毫秒至约1秒的时间范围。该退火方法的一个实例包括二次退火方法，其中在自杀化处理期间实现镍管形成的减少。在一些情况下，该方法和装置将亚秒级退火的快速加热速率与导热基板相结合，为硅晶片提供快速冷却。因此，次秒退火方法的热预算可以跨越从常规RTP退火到闪光退火工艺（包括退火的持续时间，以及峰值温度）的范围。描述其他实施例。

5. 发明授权

US07892971B2 Sub-second annealing processes for semiconductor devices 有权
标题翻译：半导体器件的次秒退火工艺
公开(公告)号：US07892971B2
公开(公告)日：2011-02-22
申请号：US12164560
申请日：2008-06-30
申请人： Jack Hwang , Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli
发明人： Jack Hwang , Sridhar Govindaraju , Karson Knutson , Harold Kennel , Aravind Killampalli
IPC分类号： H01L21/44
CPC分类号： H01L21/324 , H01L21/28518 , H01L29/665
摘要： An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.
摘要翻译：描述用于半导体制造的退火方法和装置。该方法和装置允许可以跨越热预算的退火，并且可以针对具体过程及其对应的激活能量进行定制。在一些情况下，退火方法跨越约1毫秒至约1秒的时间范围。该退火方法的一个实例包括二次退火方法，其中在自杀化处理期间实现镍管形成的减少。在一些情况下，该方法和装置将亚秒级退火的快速加热速率与导热基板相结合，为硅晶片提供快速冷却。因此，次秒退火方法的热预算可以跨越从常规RTP退火到闪光退火工艺（包括退火的持续时间，以及峰值温度）的范围。描述其他实施例。

6. 发明授权

US07790587B2 Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby 有权
标题翻译：通过超快速退火的部分再生长减少结漏电的方法和由此形成的结构
公开(公告)号：US07790587B2
公开(公告)日：2010-09-07
申请号：US11594301
申请日：2006-11-07
申请人： Jack Hwang , Sridhar Govindaraju , Seok-Hee Lee , Patrick H. Keys , Chad D. Lindfors
发明人： Jack Hwang , Sridhar Govindaraju , Seok-Hee Lee , Patrick H. Keys , Chad D. Lindfors
IPC分类号： H01L21/423
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/66575 , H01L29/6659
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal that removes defects without completely re-crystallizing the amophous region, ion implantation of electrically active dopant to a depth shallower than the remaining amorphous region, followed by a second anneal.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括通过用电中性掺杂剂的离子注入在衬底的源极/漏极区域中产生非晶区域，用第一退火进行退火，其中消除缺陷而不完全重新结晶小檗碱区域，将电活性掺杂剂离子注入到深度比剩余的非晶区浅，随后进行第二次退火。

7. 发明申请

US20080121882A1 Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed thereby 有权
标题翻译：通过超快速退火的部分再生长减少结漏电的方法和由此形成的结构
公开(公告)号：US20080121882A1
公开(公告)日：2008-05-29
申请号：US11594301
申请日：2006-11-07
申请人： Jack Hwang , Sridhar Govindaraju , Seok-Hee Lee , Patrick H. Keys , Chad D. Lindfors
发明人： Jack Hwang , Sridhar Govindaraju , Seok-Hee Lee , Patrick H. Keys , Chad D. Lindfors
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L29/66575 , H01L29/6659
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include creating an amorphous region in source/drain regions of a substrate by ion implantation with an electrically neutral dopant, annealing with a first anneal that removes defects without completely re-crystallizing the amophous region, ion implantation of electrically active dopant to a depth shallower than the remaining amorphous region, followed by a second anneal.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括通过用电中性掺杂剂的离子注入在衬底的源极/漏极区域中产生非晶区域，用第一退火进行退火，其中消除缺陷而不完全重新结晶小檗碱区域，将电活性掺杂剂离子注入到深度比剩余的非晶区浅，随后进行第二次退火。

8. 发明申请

US20070099404A1 Implant and anneal amorphization process 审中-公开
标题翻译：植入和退火非晶化过程
公开(公告)号：US20070099404A1
公开(公告)日：2007-05-03
申请号：US11261843
申请日：2005-10-28
申请人： Sridhar Govindaraju , Jack Hwang , Seok-Hee Lee , Patrick Keys , Chad Lindfors
发明人： Sridhar Govindaraju , Jack Hwang , Seok-Hee Lee , Patrick Keys , Chad Lindfors
IPC分类号： H01L21/265 , H01L21/4763
CPC分类号： H01L21/26506 , H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for improving a microelectronic device interface with an ultra-fast anneal process at an intermediate temperature that may be lower than those used in a dopant activation process. In one embodiment, a partial recrystalization of an amorphous silicon layer in the source drain region that is the precursor to the metal salicide reaction is disclosed. Source/drain regions are first amorphized using an implant process, then a metal layer is deposited in the source/drain region which reacts with the silicon in a salicide formation anneal. Amorphization reduces problems with metal diffusion that can occur during salicide formation anneal process, which typically occurs at a temperature significantly lower than the dopant activation temperature. The partial recrystalization reduces source/drain interfacial roughness, repairs amorphization-related defects, and reactivates dopants previously deactivated during the amorphization implant, thereby reducing the external resistance and leakage, as well as improving mobility and yield.
摘要翻译：一种在中间温度下用超快速退火工艺改进微电子器件界面的方法，该中间温度可低于掺杂剂激活过程中使用的那些。在一个实施例中，公开了作为金属硅化物反应的前体的源极漏极区域中的非晶硅层的部分重结晶。源极/漏极区域首先使用注入工艺非晶化，然后金属层沉积在源极/漏极区域中，其在硅化物形成退火中与硅反应。非晶化减少了在自杀化合物形成退火过程中可能发生的金属扩散的问题，其通常发生在显着低于掺杂剂活化温度的温度下。部分重结晶减少了源极/漏极界面粗糙度，修复了非晶化相关缺陷，并且在非晶化植入期间重新激化先前已去活化的掺杂剂，从而降低了外部电阻和漏电流，同时提高了迁移率和产率。

9. 发明申请

US20150179785A1 TECHNIQUES AND CONFIGURATIONS TO REDUCE TRANSISTOR GATE SHORT DEFECTS 有权
标题翻译：减少晶闸管短路缺陷的技术和配置
公开(公告)号：US20150179785A1
公开(公告)日：2015-06-25
申请号：US14137909
申请日：2013-12-20
申请人： Sridhar Govindaraju , Matthew J. Prince
发明人： Sridhar Govindaraju , Matthew J. Prince
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66
CPC分类号： H01L21/823437 , H01L21/31053 , H01L21/32115 , H01L21/76805 , H01L21/7684 , H01L21/76895 , H01L21/823431 , H01L21/823462 , H01L21/823475 , H01L23/49838 , H01L23/5329 , H01L23/535 , H01L24/16 , H01L27/0886 , H01L29/42372 , H01L29/4238 , H01L29/66795 , H01L29/785 , H01L2224/16227
摘要： Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了减少晶体管栅极短缺陷的技术和配置。在一个实施例中，一种方法包括形成多条线，其中多条线中的各条线包括栅电极材料，沉积电绝缘材料以填充各线之间的区域，然后在沉积电绝缘材料之后，至少一个独立线路的部分，以将第一晶体管器件的栅电极材料与第二晶体管器件的栅电极材料隔离。可以描述和/或要求保护其他实施例。

10. 发明申请

US20150179567A1 USING MATERIALS WITH DIFFERENT ETCH RATES TO FILL TRENCHES IN SEMICONDUCTOR DEVICES 有权
标题翻译：使用不同填充量的材料在半导体器件中填充TRENCHES
公开(公告)号：US20150179567A1
公开(公告)日：2015-06-25
申请号：US14137497
申请日：2013-12-20
申请人： Sridhar Govindaraju , Anindya Dasgupta , Rohit Grover
发明人： Sridhar Govindaraju , Anindya Dasgupta , Rohit Grover
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5226 , H01L21/76804 , H01L21/76831 , H01L21/76865 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.
摘要翻译：实施例包括金属互连结构，包括：基底上的电介质层; 在所述介电层中的开口，其中所述开口具有开口侧壁并且暴露所述衬底和附加互连结构中的至少一个的导电区域; 在导电区域和开口侧壁上的第一原子层沉积（ALD）层; 在第一ALD层的一部分上的第二ALD层和在开口内和第一ALD层上的第三ALD层。本文描述了其它实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式