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1. 发明申请

US20140056094A1 WORD-LINE ACTIVATION CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：字线激活电路，半导体存储器件和半导体集成电路
公开(公告)号：US20140056094A1
公开(公告)日：2014-02-27
申请号：US13946850
申请日：2013-07-19
申请人： PANASONIC CORPORATION
发明人： Tadashi NITTA , Tsuyoshi KOIKE
IPC分类号： G11C11/413 , G11C11/418
CPC分类号： G11C11/413 , G11C8/08 , G11C11/418
摘要： In a state where a signal (IN) is at “H” and an NMOS transistor (403) is on, when a signal (PCLK) changes to “H” and a PMOS transistor (401) turns off, an output node (N1) becomes coupled to a word-line activation signal (WACTCLK) via the NMOS transistor (403). When the word-line activation signal (WACTCLK) changes to “L,” a word line signal (MWL) changes to “L.” Since the signal (PCLK) is at “H” and the NMOS transistor (405) is on, this NMOS transistor (405) can assist discharging of the word-line activation signal (WACTCLK) to a ground voltage.
摘要翻译：在信号（IN）为“H”且NMOS晶体管（403）导通的状态下，当信号（PCLK）变为“H”并且PMOS晶体管（401）截止时，输出节点）经由NMOS晶体管（403）耦合到字线激活信号（WACTCLK）。当字线激活信号（WACTCLK）变为“L”时，字线信号（MWL）变为“L”。由于信号（PCLK）处于“H”并且NMOS晶体管（405）导通，所以该NMOS晶体管（405）可以帮助字线激活信号（WACTCLK）放电到接地电压。

2. 发明申请

US20140036613A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20140036613A1
公开(公告)日：2014-02-06
申请号：US14044861
申请日：2013-10-02
申请人： Panasonic Corporation
发明人： Tsuyoshi KOIKE , Noriaki NARUMI
IPC分类号： G11C8/10 , H03K17/22
CPC分类号： G11C8/10 , H03K17/223 , H03K19/0963
摘要： There are included first and second dynamic circuits and first and second transistors. The first dynamic circuit keeps a first dynamic node at a first level when a plurality of input signals is in a first state, and switches the first dynamic node between the first level and a second level in accordance with a first clock signal when the plurality of input signals is in a second state. The second dynamic circuit includes a compensating circuit that is provided between the second dynamic node and a second power supply and connects the second dynamic node to the second power supply so as to compensate the level of the second dynamic node when the plurality of input signals is in the second state and the first dynamic node is at a level other than the first level.
摘要翻译：包括第一和第二动态电路以及第一和第二晶体管。当多个输入信号处于第一状态时，第一动态电路将第一动态节点保持在第一电平，并且当多个输入信号处于第一状态时，第一动态节点根据第一时钟信号在第一电平和第二电平之间切换输入信号处于第二状态。第二动态电路包括：补偿电路，其设置在第二动态节点和第二电源之间，并且将第二动态节点连接到第二电源，以便当多个输入信号为在第二状态和第一动态节点处于除第一级之外的水平。

3. 发明申请

US20130051163A1 DATA TRANSMISSION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
标题翻译：数据传输电路和包括其的半导体存储器件
公开(公告)号：US20130051163A1
公开(公告)日：2013-02-28
申请号：US13661711
申请日：2012-10-26
申请人： PANASONIC CORPORATION
发明人： Tsuyoshi KOIKE
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C29/026 , G11C29/023 , G11C29/028
摘要： The data transmission circuit includes: a plurality of local bit line pairs through which data is read simultaneously; a plurality of voltage change detection circuits provided for the plurality of local bit line pairs; a global bit line pair; a plurality of column selection circuits configured to select one of the local bit line pairs and connect the selected local bit line pair to the global bit line pair; and a sense amplifier connected to the global bit line pair. The sense amplifier is controlled by a sense amplifier activation signal to which the outputs of the plurality of voltage change detection circuits are connected, whereby the voltage of a selected read data line pair is amplified using discharge of a non-selected read data line pair, to achieve high-speed read.
摘要翻译：数据传输电路包括：同时读取数据的多个局部位线对; 为多个局部位线对设置的多个电压变化检测电路; 全局位线对; 多个列选择电路，被配置为选择本地位线对中的一个并将所选择的局部位线对连接到全局位线对; 以及连接到全局位线对的读出放大器。感测放大器由读出放大器激活信号控制，多个电压变化检测电路的输出端连接到读出放大器激活信号，由此，使用非选择的读取数据线对的放电来放大所选择的读取数据线对的电压，实现高速读取。

4. 发明申请

US20140028362A1 INPUT CIRCUIT 有权
标题翻译：输入电路
公开(公告)号：US20140028362A1
公开(公告)日：2014-01-30
申请号：US14040519
申请日：2013-09-27
申请人： PANASONIC CORPORATION
发明人： Tsuyoshi KOIKE , Shigeo HOUMURA
IPC分类号： H03K3/037
CPC分类号： H03K3/0375 , G01R31/318541 , G11C29/1201 , G11C29/32 , G11C2029/3202
摘要： A combination circuit generates first and second internal signals according to first and second input signals, respectively. A first master latch circuit selectively captures and holds a scan-in signal and the first internal signal, and generates a first output signal and a first intermediate signal based on the signals thus captured and held. A first slave latch circuit selectively captures and holds the first intermediate signal and the second internal signal, and generates a second output signal and a scan-out signal based on the signals thus captured and held. This arrangement reduces a circuit scale and power consumption of the input circuited provided in a semiconductor integrated circuit to which a scan path test method is applied.
摘要翻译：组合电路分别根据第一和第二输入信号产生第一和第二内部信号。第一主锁存电路选择性地捕获并保持扫描信号和第一内部信号，并且基于这样捕获和保持的信号产生第一输出信号和第一中间信号。第一从锁存电路选择性地捕获并保持第一中间信号和第二内部信号，并且基于如此捕获和保持的信号产生第二输出信号和扫描输出信号。这种布置减少了应用扫描路径测试方法的半导体集成电路中提供的输入电路的电路规模和功耗。

5. 发明申请

US20130028032A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130028032A1
公开(公告)日：2013-01-31
申请号：US13628574
申请日：2012-09-27
申请人： PANASONIC CORPORATION
发明人： Tsuyoshi KOIKE , Youji NAKAI
IPC分类号： G11C7/12
CPC分类号： G11C7/18 , G11C7/12 , G11C11/413 , G11C2207/002
摘要： A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.
摘要翻译：第一写入晶体管具有连接到电源节点的源极，连接到第一局部位线的漏极和连接到第二写入全局位线的栅极。第二写入晶体管具有连接到电源节点的源极，连接到第二局部位线的漏极和连接到第一写入全局位线的栅极。第三写入晶体管具有连接到第一写入全局位线的源极，连接到第一局部位线的漏极和接收第一控制信号的栅极。第四写入晶体管具有连接到第二写入全局位线的源极，连接到第二局部位线的漏极和接收第一控制信号的栅极。读取电路连接到第一和第二本地位线以及第一和第二读取全局位线。

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