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1. 发明授权

US08946826B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08946826B2
公开(公告)日：2015-02-03
申请号：US14179556
申请日：2014-02-13
申请人： Panasonic Corporation
发明人： Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
IPC分类号： H01L27/092 , H01L27/02 , H01L27/118 , H01L21/8238
CPC分类号： H01L27/11807 , H01L21/823892 , H01L27/0207 , H01L27/0928 , H01L27/11898 , H01L2027/11866 , H01L2027/11881 , H01L2027/1189
摘要： A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
摘要翻译：在电池阵列的N型阱区域中提供阱电位区域。设置在水平方向上的井电位供给区域的两侧的相邻门和设置在其两侧的相邻门以相同的间距设置。此外，相邻单元阵列包括四个栅极，每个栅极在垂直方向上与相邻栅极相对。换句话说，维持在阱电位供给区域的外围的栅极图案的形状的规则性。

2. 发明授权

US08791507B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08791507B2
公开(公告)日：2014-07-29
申请号：US13846514
申请日：2013-03-18
申请人： Panasonic Corporation
发明人： Kazuyuki Nakanishi , Masaki Tamaru
IPC分类号： H01L27/118
CPC分类号： H01L27/0207
摘要： A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.
摘要翻译：半导体器件的布局能够可靠地降低由于光学邻近效应引起的栅极长度的变化，并且能够实现灵活的布局设计。单元（C1）的栅极图案（G1，G2，G3）以相同的间距排列，并且栅极图案的末端（e1，e2，e3）位于与Y方向相同的位置，相同宽度的X方向。电池（C2）的栅极图案（G4）具有在Y方向朝向电池单元（C1）突出的突出部分（4b），并且突出部分（4b）形成相对的末端（eo1，eo2，eo3）。相对的末端（eo1，eo2，eo3）以与栅极图案（G1，G2，G3）相同的间距配置在与Y方向相同的位置，并且在X方向上具有相同的宽度。

3. 发明授权

US08748987B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08748987B2
公开(公告)日：2014-06-10
申请号：US14062450
申请日：2013-10-24
申请人： Panasonic Corporation
发明人： Tomoaki Ikegami , Kazuyuki Nakanishi , Masaki Tamaru
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L27/0248 , H01L27/0255 , H01L27/0629 , H01L27/11898
摘要： A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
摘要翻译：标准单元具有沿Y方向延伸的栅极图案，并且在X方向上以等间距排列。栅极图案的端部位于Y方向上的相同位置，并且在X方向上具有相等的宽度。除了用作二极管的扩散层之外，二极管单元位于Y方向上的标准单元旁边，并且包括与端部相对的栅极图案形成的多个相对端部。

4. 发明授权

US09362264B2 Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array 有权
标题翻译：包括多个单元阵列的半导体器件，所述多个单元阵列包括提供在单元阵列的阱区上的阱电位区和相邻的虚拟栅
公开(公告)号：US09362264B2
公开(公告)日：2016-06-07
申请号：US14576158
申请日：2014-12-18
申请人： PANASONIC CORPORATION
发明人： Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
IPC分类号： H01L27/02 , H01L27/092 , H01L21/8238 , H01L27/118
CPC分类号： H01L27/11807 , H01L21/823892 , H01L27/0207 , H01L27/0928 , H01L27/11898 , H01L2027/11866 , H01L2027/11881 , H01L2027/1189
摘要： A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
摘要翻译：在电池阵列的N型阱区域中提供阱电位区域。设置在水平方向上的井电位供给区域的两侧的相邻门和设置在其两侧的相邻门以相同的间距设置。此外，相邻单元阵列包括四个栅极，每个栅极在垂直方向上与相邻栅极相对。换句话说，维持在阱电位供给区域的外围的栅极图案的形状的规则性。

5. 发明授权

US09099447B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09099447B2
公开(公告)日：2015-08-04
申请号：US13659229
申请日：2012-10-24
申请人： PANASONIC CORPORATION
发明人： Masaki Tamaru
IPC分类号： H01L21/02 , H01L23/48 , H01L23/52 , H01L23/40 , H01L23/485 , H01L21/768 , H01L27/02 , H01L27/118
CPC分类号： H01L27/11807 , H01L21/76895 , H01L23/485 , H01L27/0207 , H01L29/1079 , H01L2027/11829 , H01L2027/11861 , H01L2027/11866 , H01L2027/11875 , H01L2924/0002 , H01L2924/00
摘要： A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.
摘要翻译：局部互连形成为与杂质扩散区的上表面接触并且延伸到潜在的电源互连以下。接触孔将局部互连电耦合到电源互连。与杂质扩散区的上表面接触形成的局部互连用于将杂质扩散区电耦合到电势互连。

6. 发明授权

US09343461B2 Semiconductor device including a local wiring connecting diffusion regions 有权
标题翻译：包括连接扩散区域的局部布线的半导体器件
公开(公告)号：US09343461B2
公开(公告)日：2016-05-17
申请号：US14489188
申请日：2014-09-17
申请人： PANASONIC CORPORATION
发明人： Hiroyuki Shimbo , Masaki Tamaru
IPC分类号： H01L27/092 , H01L21/8238 , H01L27/02 , H01L23/538 , H01L29/423
CPC分类号： H01L27/0928 , H01L21/823871 , H01L23/5386 , H01L27/0207 , H01L29/4232 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.
摘要翻译：半导体器件具有沿第一方向延伸的第一导电类型区域和沿第一方向延伸的第二导电类型区域。第一导电类型区域和第二导电类型区域沿垂直于第一方向的第二方向交替布置。半导体器件包括形成在第一导电类型区域中的第一杂质扩散区域，与第一导电类型区域连接并沿第二方向延伸的第一局部布线，形成在第一局部布线上方的第一电位供应布线，以及用于将第一局部布线连接到第一电位布线的第一接触孔。

7. 发明授权

US09147652B2 Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit 有权
标题翻译：标准单元的布局结构，标准单元库和半导体集成电路的布局结构
公开(公告)号：US09147652B2
公开(公告)日：2015-09-29
申请号：US14281662
申请日：2014-05-19
申请人： PANASONIC CORPORATION
发明人： Nana Okamoto , Masaki Tamaru , Hidetoshi Nishimura
IPC分类号： H01L27/118 , H01L23/498 , H01L27/02
CPC分类号： H01L23/49827 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
摘要翻译：在不需要电路的逻辑运算的包括截止晶体管126,127的标准单元的布局结构中，虚设通孔触点116,117分别设置在截止晶体管126,127的杂质扩散区域103,106上。虚拟金属互连122,123分别经由触点116,117连接到虚拟电路。因此，降低了半导体集成电路的制造成本的原因之一是通孔接点的密度变化减小，从而改善了通孔接点的制造缺陷。

8. 发明授权

US08946824B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08946824B2
公开(公告)日：2015-02-03
申请号：US14253551
申请日：2014-04-15
申请人： Panasonic Corporation
发明人： Tomoaki Ikegami , Kazuyuki Nakanishi , Masaki Tamaru
IPC分类号： H01L23/62 , H01L27/06 , H01L27/02 , H01L27/118
CPC分类号： H01L27/0207 , H01L27/0248 , H01L27/0255 , H01L27/0629 , H01L27/11898
摘要： A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.
摘要翻译：标准单元具有沿Y方向延伸的栅极图案，并且在X方向上以等间距排列。栅极图案的端部位于Y方向上的相同位置，并且在X方向上具有相等的宽度。除了用作二极管的扩散层之外，二极管单元位于Y方向上的标准单元旁边，并且包括与端部相对的栅极图案形成的多个相对端部。

9. 发明授权

US08598668B2 Semiconductor device 有权
公开(公告)号：US08598668B2
公开(公告)日：2013-12-03
申请号：US13767396
申请日：2013-02-14
申请人： Panasonic Corporation
发明人： Tomoaki Ikegami , Kazuyuki Nakanishi , Masaki Tamaru
IPC分类号： H01L23/62
CPC分类号： H01L27/0207 , H01L27/0248 , H01L27/0255 , H01L27/0629 , H01L27/11898
摘要： A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

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