专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06366467B1 Dual-socket interposer and method of fabrication therefor 有权
公开(公告)号：US06366467B1
公开(公告)日：2002-04-02
申请号：US09540046
申请日：2000-03-31
申请人： P. R. Patel , Yuan-Liang Li , David G. Figueroa , Shamala Chickamenahalli , Huong T. Do
发明人： P. R. Patel , Yuan-Liang Li , David G. Figueroa , Shamala Chickamenahalli , Huong T. Do
IPC分类号： H05K702
CPC分类号： H05K1/141 , H01L2224/16225 , H01L2924/00014 , H01L2924/15192 , H05K1/0262 , H05K3/368 , H05K7/1092 , H05K2201/049 , H05K2201/10196 , H05K2201/10325 , H05K2201/10689 , H05K2201/10704 , H01L2224/0401
摘要： An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.

2. 发明授权

US06469908B2 Dual-socket interposer and method of fabrication therefor 失效
标题翻译：双插座插入器及其制造方法
公开(公告)号：US06469908B2
公开(公告)日：2002-10-22
申请号：US10076893
申请日：2002-02-14
申请人： P. R. Patel , Yuan-Liang Li , David G. Figueroa , Shamala Chickamenahalli , Huong T. Do
发明人： P. R. Patel , Yuan-Liang Li , David G. Figueroa , Shamala Chickamenahalli , Huong T. Do
IPC分类号： H05K710
CPC分类号： H05K1/141 , H01L2224/16225 , H01L2924/00014 , H01L2924/15192 , H05K1/0262 , H05K3/368 , H05K7/1092 , H05K2201/049 , H05K2201/10196 , H05K2201/10325 , H05K2201/10689 , H05K2201/10704 , H01L2224/0401
摘要： An interposer includes two separate sets of pins, and inserts into two sockets on a printed circuit board. One set of pins supplies power to a step down converter (SDC) mounted on the interposer. The second set of pins provide inputs and outputs to an integrated circuit mounted on the interposer. One or more conductive traces in or on the interposer electrically connect an output of the SDC to an input of the integrated circuit, thus supplying regulated power to the integrated circuit through the interposer. The SDC and integrated circuit can be directly mounted on the interposer, or either or both can be mounted on packages that connect to the interposer. The SDC and integrated circuit can be flip chips or can be connected to the interposer or package using wirebonds. The packages can be pinned or connectable by solder bumps.
摘要翻译：插入器包括两组独立的引脚，并插入到印刷电路板上的两个插槽中。一组引脚为安装在插入器上的降压转换器（SDC）供电。第二组引脚为安装在插入器上的集成电路提供输入和输出。插入器中或之上的一个或多个导电迹线将SDC的输出电连接到集成电路的输入，从而通过插入器向集成电路提供稳压电力。 SDC和集成电路可以直接安装在插入器上，或者两者都可以安装在连接到插入器的封装上。 SDC和集成电路可以是倒装芯片，也可以使用引线连接到插入器或封装。封装可以通过焊料凸块固定或连接。

3. 发明授权

US06920051B2 Hybrid capacitor, circuit, and system 失效
标题翻译：混合电容，电路和系统
公开(公告)号：US06920051B2
公开(公告)日：2005-07-19
申请号：US10155628
申请日：2002-05-24
申请人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
发明人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
IPC分类号： H01L23/64 , H05K1/14 , H05K1/16 , H05K1/18
CPC分类号： H01L23/642 , H01L2924/0002 , H01L2924/15312 , H01L2924/19105 , H05K1/141 , H05K1/162 , Y10T29/435 , H01L2924/00
摘要： A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.
摘要翻译：与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。分立电容器电连接到从导电层到封装表面的触点。在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

4. 发明授权

US06446317B1 Hybrid capacitor and method of fabrication therefor 失效
标题翻译：混合电容器制造方法
公开(公告)号：US06446317B1
公开(公告)日：2002-09-10
申请号：US09540705
申请日：2000-03-31
申请人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
发明人： David G. Figueroa , Yuan-Liang Li , Huong T. Do
IPC分类号： H01G700
CPC分类号： H01L23/642 , H01L2924/0002 , H01L2924/15312 , H01L2924/19105 , H05K1/141 , H05K1/162 , Y10T29/435 , H01L2924/00
摘要： A hybrid capacitor associated with an integrated circuit package provides multiple levels of excess, off-chip capacitance to die loads. The hybrid capacitor includes a low inductance, parallel plate capacitor embedded within the package, and electrically connected to a second source of off-chip capacitance. The parallel plate capacitor is disposed underneath a die, and includes a top conductive layer, a bottom conductive layer, and a thin dielectric layer that electrically isolates the top and bottom layers. The second source of off-chip capacitance is a set of self-aligned via capacitors, and/or one or more discrete capacitors, and/or an additional parallel plate capacitor. Each of the self-aligned via capacitors is embedded within the package, and has an inner conductor and an outer conductor. The inner conductor is electrically connected to either the top or bottom conductive layer, and the outer conductor is electrically connected to the other conductive layer. The discrete capacitors are electrically connected to contacts from the conductive layers to the surface of the package. During operation, one of the conductive layers of the low inductance parallel plate capacitor provides a ground plane, while the other conductive layer provides a power plane.
摘要翻译：与集成电路封装相关联的混合电容为裸片负载提供多级多余的片外电容。混合电容器包括嵌入在封装内的低电感并联板电容器，并且电连接到片外电容的第二源极。平行板电容器设置在管芯下方，并且包括顶部导电层，底部导电层和电绝缘顶层和底层的薄介电层。片外电容的第二个源是一组自对准通孔电容器和/或一个或多个分立电容器和/或附加的平行板电容器。每个自对准通孔电容器嵌入在封装内，并具有内部导体和外部导体。内部导体电连接到顶部或底部导电层，并且外部导体电连接到另一个导电层。分立电容器电连接到从导电层到封装表面的触点。在操作期间，低电感平行板电容器的导电层之一提供接地平面，而另一导电层提供电源平面。

5. 发明授权

US06483692B2 Capacitor with extended surface lands and method of fabrication therefor 失效
公开(公告)号：US06483692B2
公开(公告)日：2002-11-19
申请号：US09741302
申请日：2000-12-19
申请人： David G. Figueroa , Huong T. Do , Jorge Pedro Rodriguez , Michael Walk
发明人： David G. Figueroa , Huong T. Do , Jorge Pedro Rodriguez , Michael Walk
IPC分类号： H01G220
CPC分类号： H01G2/065 , H01L2924/15311
摘要： A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).

6. 发明授权

US06532143B2 Multiple tier array capacitor 有权
标题翻译：多层阵列电容
公开(公告)号：US06532143B2
公开(公告)日：2003-03-11
申请号：US09751612
申请日：2000-12-29
申请人： David G. Figueroa , Kishore K. Chakravorty , Huong T. Do , Larry Eugene Mosley , Jorge Pedro Rodriguez , Ken Brown
发明人： David G. Figueroa , Kishore K. Chakravorty , Huong T. Do , Larry Eugene Mosley , Jorge Pedro Rodriguez , Ken Brown
IPC分类号： H01G430
CPC分类号： H01G4/30 , H01L23/642 , H01L2224/16225 , H01L2924/00014 , H05K1/0298 , H05K1/162 , H01L2224/0401
摘要： A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, FIGS. 3, 12, 13), which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, FIGS. 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, FIGS. 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tiers (1310, 1312, FIG. 13) are located in a center region (1404, FIG. 14) of the capacitor, and one or more other tiers (1380, FIG. 13) are located in a peripheral region (1408, FIG. 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, FIG. 13) of patterned conductive material. The capacitors of the various embodiments can be used as discrete devices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricated within the housing.
摘要翻译：电容器包括多层（302,304,306,1210,1212,1310,1312,1380，图3,12,13），其以不同的电感值向负载提供电容。每个层包括被介电材料层隔开的图案化导电材料的多层（311-325,1220,1222,1320,1322,1382，图3,12,13）。在一个实施例中，层是沿垂直方向堆叠的，并且通过延伸穿过一些或所有层的通孔（330,332,334,1230,1232，图3,12）电连接。在另一个实施例中，一个或多个层（1310,1312，图13）位于电容器的中心区域（1404，图14）中，并且一个或多个其他层（图13中的1380）位于电容器的外围区域（1408，图14）。在该实施例中，中心层和外围层通过图案化导电材料的一个或多个附加层（1370，图13）电连接。各种实施例的电容器可以用作可安装在壳体（例如，封装，插入件，插座或PC板）中或嵌入其中的分立器件，或者它们可以一体地制造在壳体内。

7. 发明授权

US07518248B2 Inductive filters and methods of fabrication therefor 有权
标题翻译：电感式滤波器及其制造方法
公开(公告)号：US07518248B2
公开(公告)日：2009-04-14
申请号：US11462611
申请日：2006-08-04
申请人： Yuan-Liang Li , David G. Figueroa
发明人： Yuan-Liang Li , David G. Figueroa
IPC分类号： H01L23/52
CPC分类号： H01F17/0033 , H01F41/041 , H01L23/49822 , H01L23/49838 , H01L2224/16 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15312 , H05K1/115 , H05K1/165 , H05K3/06 , H05K3/42 , H05K2201/086 , H05K2201/097 , H05K2201/1006 , H05K2203/0723 , H01L2224/0401
摘要： A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.
摘要翻译：一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。在一些实施例中，板包括嵌入的铁磁材料图案。电介质板的孔和顶表面和底表面之间具有导电材料。选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

8. 发明授权

US07492605B2 Power plane to reduce voltage difference between connector power pins 失效
标题翻译：电源平面，以减少连接器电源引脚之间的电压差
公开(公告)号：US07492605B2
公开(公告)日：2009-02-17
申请号：US11473359
申请日：2006-06-22
申请人： Yuan-Liang Li , Jayashree Kar , David G. Figueroa , Dong Zhong
发明人： Yuan-Liang Li , Jayashree Kar , David G. Figueroa , Dong Zhong
IPC分类号： H05K1/11 , H05K1/00
CPC分类号： H05K1/0265 , H05K1/0254 , H05K2201/044 , H05K2201/0784 , H05K2201/093 , H05K2201/0969
摘要： A power plane including a supply power pin receptacle, a first connector power pin receptacle, and a second power pin receptacle, where a first electrical resistance between the supply power pin receptacle and the first connector power pin receptacle is substantially equal to a second electrical resistance between the supply power pin receptacle and the second connector power pin receptacle.
摘要翻译：包括供电电源插座，第一连接器电源插座和第二电源插座的电力平面，其中电源电极插座和第一连接器电源插座之间的第一电阻基本上等于第二电阻在电源插座和第二连接器电源插座之间。

9. 发明授权

US07176565B2 Capacitors having separate terminals on three or more sides 失效
标题翻译：电容器在三面或三面以上具有独立的端子
公开(公告)号：US07176565B2
公开(公告)日：2007-02-13
申请号：US10006188
申请日：2001-12-03
申请人： Yuan-Liang Li , David G. Figueroa , Chee-Yee Chung
发明人： Yuan-Liang Li , David G. Figueroa , Chee-Yee Chung
IPC分类号： H01L23/34
CPC分类号： H01G4/232
摘要： A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.
摘要翻译：多层电容器包括在至少三个侧面上以及多达六个侧面的分开的端子。根据目标应用，电容器可以以大量不同的配置，类型和尺寸制造。设置在电容器的不同侧上的单独的端子可以容易地耦合到各种不同的相邻导体，例如模具端子（包括无扰动端子或条），IC封装端子（包括焊盘或条），以及端子相邻的分立元件。还描述了制造方法以及将电容器应用于电子组件。

10. 发明授权

US06992387B2 Capacitor-related systems for addressing package/motherboard resonance 有权
标题翻译：用于寻址封装/主板谐振的电容器相关系统
公开(公告)号：US06992387B2
公开(公告)日：2006-01-31
申请号：US10602096
申请日：2003-06-23
申请人： Jennifer A. Hester , Yuan-Liang Li , Michael M. Desmith , David G. Figueroa , Dong Zhong
发明人： Jennifer A. Hester , Yuan-Liang Li , Michael M. Desmith , David G. Figueroa , Dong Zhong
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H05K1/114 , H01G4/385 , H01L23/49838 , H01L23/642 , H01L2224/16 , H01L2224/16227 , H01L2924/00014 , H01L2924/01021 , H01L2924/01057 , H01L2924/15312 , H01L2924/19106 , H01L2924/3011 , H05K1/0231 , H05K2201/09263 , H05K2201/09345 , H05K2201/0979 , H05K2201/10636 , Y02P70/611 , H01L2224/0401
摘要： According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.
摘要翻译：根据一些实施例，器件包括电耦合到与第一极性相关联的第一端子的第一导电平面和与第一极性相关联的第二端子，电耦合到与第二极性相关联的第三端子的第二导电平面，以及设置在所述第一导电平面和所述第二导电平面之间的电介质。在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以是基本不相似的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式