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    • 6. 发明授权
    • Semiconductor device and electrical circuit device using thereof
    • 半导体装置及其电路装置
    • US07768066B2
    • 2010-08-03
    • US12179549
    • 2008-07-24
    • Hidekatsu OnoseHiroyuki Takazawa
    • Hidekatsu OnoseHiroyuki Takazawa
    • H01L29/94
    • H01L29/7828H01L25/18H01L29/0623H01L29/0696H01L29/1608H01L29/66068H01L29/7391H01L2924/0002H01L2924/00
    • A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N− type drift layer and lower than that of the P type body layer.
    • UMOSFET能够降低阈值电压并产生大的饱和电流。 根据本发明的典型的UMOSFET包括:构成漏极层的N +型SiC衬底; 与漏极层接触并构成漂移层的N型SiC层; 形成在所述漂移层上并且是半导体层的P型体层; 构成源极层的N +型SiC层; 从源极层延伸到放置在漂移层中的预定位置的沟槽; 设置在沟槽的底部周围和外侧的P型电场弛豫区域; 以及从N +型源极层向P型电场弛豫区域延伸并且杂质浓度高于N型漂移层的杂质浓度并低于P型体层的沟道区域。