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1. 发明申请

US20180173625A1 IMPLEMENTING ATOMIC PRIMITIVES USING CACHE LINE LOCKING 审中-公开
公开(公告)号：US20180173625A1
公开(公告)日：2018-06-21
申请号：US15841974
申请日：2017-12-14
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , A. Joseph Hoane
IPC分类号： G06F12/0817 , G06F9/52 , G06F9/30 , G06F9/54 , G06F12/0811
摘要： A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.

2. 发明授权

US09940129B2 Computer processor with register direct branches and employing an instruction preload structure 有权
公开(公告)号：US09940129B2
公开(公告)日：2018-04-10
申请号：US15087269
申请日：2016-03-31
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F12/08 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
CPC分类号： G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
摘要： A computer processor with register direct branches and employing an instruction preload structure is disclosed. The computer processor may include a hierarchy of memories comprising a first memory organized in a structure having one or more entries for one or more addresses corresponding to one or more instructions. The one or more entries of the one or more addresses may have a starting address. The structure may have one or more locations for storing the one or more instructions. The computer processor may include one or more registers to which one or more corresponding instruction addresses are writable. The computer processor may include processing logic. In response to the processing logic writing the one or more instruction addresses to the one or more registers, the processing logic may to pre-fetch the one or more instructions of a linear sequence of instructions from a first memory level of the hierarchy of memories into a second memory level of the hierarchy of memories beginning at the starting address. At least one address of the one or more addresses may be the contents of a register of the one or more registers.

3. 发明授权

US10719451B2 Variable translation-lookaside buffer (TLB) indexing 有权
公开(公告)号：US10719451B2
公开(公告)日：2020-07-21
申请号：US15868513
申请日：2018-01-11
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , A. Joseph Hoane , Lei Wang , Gary Nacer , Aaron G. Milbury , Enrique A. Barria , Paul Hurtley
IPC分类号： G06F12/1027 , G06F12/1036 , G06F12/1009 , G06F12/0864
摘要： A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

4. 发明申请

US20160314074A1 COMPUTER PROCESSOR THAT IMPLEMENTS PRE-TRANSLATION OF VIRTUAL ADDRESSES 审中-公开
标题翻译：计算机处理器实现虚拟地址的预翻译
公开(公告)号：US20160314074A1
公开(公告)日：2016-10-27
申请号：US15087150
申请日：2016-03-31
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
摘要： A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
摘要翻译：公开了实现虚拟地址的预翻译的计算机处理器。计算机处理器可以包括包括一个或多个寄存器的寄存器文件。计算机处理器可以包括处理逻辑。处理逻辑可以接收一个值以存储在一个或多个寄存器的寄存器中。处理逻辑可以将该值存储在寄存器中。处理逻辑可以将接收的值指定为虚拟地址，虚拟地址具有对应的虚拟基页号。处理逻辑可以将虚拟基页编号转换为对应的真实基页编号和对应于与虚拟基页编号相邻的零个或多个虚拟页码的零个或多个实际页号。处理逻辑还可以在一个或多个寄存器的寄存器中存储真实的基页号码和零个或多个实际页码。

5. 发明申请

US20180203806A1 VARIABLE TRANSLATION-LOOKASIDE BUFFER (TLB) INDEXING 审中-公开
公开(公告)号：US20180203806A1
公开(公告)日：2018-07-19
申请号：US15868513
申请日：2018-01-11
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , A. Joseph Hoane , Lei Wang , Gary Nacer , Aaron G. Milbury , Enrique A. Barria , Paul Hurtley
IPC分类号： G06F12/1027 , G06F12/1009
摘要： A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

6. 发明申请

US20160313996A1 COMPUTER PROCESSOR WITH ADDRESS REGISTER FILE 审中-公开
标题翻译：具有地址寄存器文件的计算机处理器
公开(公告)号：US20160313996A1
公开(公告)日：2016-10-27
申请号：US15086711
申请日：2016-03-31
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F9/30 , G06F3/06
摘要： A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
摘要翻译：公开了一种具有地址寄存器文件的计算机处理器。计算机处理器可以包括存储器。计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及添加在指令中编码的位移值。

7. 发明申请

US20160313995A1 COMPUTER PROCESSOR WITH INDIRECT ONLY BRANCHING 审中-公开
标题翻译：具有间接分支的计算机处理器
公开(公告)号：US20160313995A1
公开(公告)日：2016-10-27
申请号：US15086752
申请日：2016-03-31
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F9/30
CPC分类号： G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/1027 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/6028 , G06F2212/651 , G06F2212/684
摘要： A computer processor with indirect only branching is disclosed. The computer processor may include one or more target registers. The computer processor may include processing logic in signal communication with the one or more target registers. The processing logic may execute a non-interrupting branch instruction based on a value stored in a target register of the one or more target registers. The non-interrupting branch instruction may use the one or more target registers to specify a destination address of a branch specified by the non-interrupting branch instruction.
摘要翻译：公开了一种仅间接分支的计算机处理器。计算机处理器可以包括一个或多个目标寄存器。计算机处理器可以包括与一个或多个目标寄存器进行信号通信的处理逻辑。处理逻辑可以基于存储在一个或多个目标寄存器的目标寄存器中的值来执行非中断分支指令。非中断分支指令可以使用一个或多个目标寄存器来指定由非中断分支指令指定的分支的目的地地址。

8. 发明授权

US11157407B2 Implementing atomic primitives using cache line locking 有权
公开(公告)号：US11157407B2
公开(公告)日：2021-10-26
申请号：US15841974
申请日：2017-12-14
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , A. Joseph Hoane
IPC分类号： G06F12/0817 , G06F9/30 , G06F12/084 , G06F12/0895 , G06F9/52 , G06F9/54 , G06F12/0811
摘要： A processor comprising a cache, the cache comprising a cache line, an execution unit to execute an atomic primitive to responsive to executing a read instruction to retrieve a data item from a memory location, cause to store a copy of the data item in the cache line, execute a lock instruction to lock the cache line to the processor, execute at least one instruction while the cache line is locked to the processor, and execute an unlock instruction to cause the cache controller to release the cache line from the processor.

9. 发明授权

US10169039B2 Computer processor that implements pre-translation of virtual addresses 有权
公开(公告)号：US10169039B2
公开(公告)日：2019-01-01
申请号：US15087150
申请日：2016-03-31
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC分类号： G06F12/08 , G06F12/10 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
摘要： A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.

10. 发明申请

US20180203703A1 IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH 审中-公开
公开(公告)号：US20180203703A1
公开(公告)日：2018-07-19
申请号：US15868497
申请日：2018-01-11
申请人： Optimum Semiconductor Technologies, Inc.
发明人： Mayan Moudgill , Gary Nacer , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan
IPC分类号： G06F9/38 , G06F9/30
摘要： A processor includes a plurality of physical registers and a processor core, communicatively coupled to the plurality of physical registers, the processor core to execute a process comprising a plurality of instructions to responsive to issuance of a call instruction for out-of-order execution, identify, based on a head pointer of the plurality of physical registers, a first physical register of the plurality of physical registers, store a return address in the first physical register, wherein the first physical register is associated with a first identifier, store, based on an out-of-order pointer of a call stack associated with the process, the first identifier in a first entry of the call stack, and increment, modulated by a length of the call stack, the out-of-order pointer of the call stack to point to a second entry of the call stack.

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