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1. 发明申请

US20100002948A1 IMAGE ENHANCEMENT 失效
标题翻译：图像增强
公开(公告)号：US20100002948A1
公开(公告)日：2010-01-07
申请号：US12443728
申请日：2007-10-02
申请人： Om Prakash Gangwal , Eric Peter Funke , Christiaan Varekamp , Mickael Stephane Bernard George Bouvier
发明人： Om Prakash Gangwal , Eric Peter Funke , Christiaan Varekamp , Mickael Stephane Bernard George Bouvier
IPC分类号： G06K9/40
CPC分类号： G06T7/579 , H04N13/128 , H04N13/261
摘要： The present invention relates to an image enhancement unit and a method of enhancing a first structure (S1) of samples into a second structure (S2) of samples, the first and the second structure both representing a first property of a scene and having a first resolution, based on a third structure (S3) of samples representing a second property and having the first resolution, the first property and the second property respectively representing different properties of substantially the same scene. The method comprising generating a fourth structure (S4) of samples representing the first property, the fourth structure (S4) of samples having a second resolution lower than the first resolution, by down-scaling first samples of the first structure (S1) of samples to form the samples of the fourth structure (S4) of samples. The method further comprising up-scaling the fourth structure (S4) of samples representing the first property, into the second structure (S2) based on the third structure (S3) of samples, the up-scaling comprising assigning weight factors to respective samples of the fourth structure (S4) of samples based on samples of the third structure (S3) of samples; and computing samples of the second structure (S2) of samples using the samples of the fourth structure (S4) of samples and their respectively assigned weight factors. The invention further relates to an image-processing unit comprising an image enhancement unit according to the invention as well as to a computer program product.
摘要翻译：本发明涉及一种将样本的第一结构（S1）增强为样本的第二结构（S2）的图像增强单元和方法，所述第一和第二结构都表示场景的第一属性，并且具有第一分辨率，基于代表第二属性并具有第一分辨率的第三结构（S3），第一属性和第二属性分别表示基本上相同的场景的不同属性。该方法包括：通过对样本的第一结构（S1）的第一样本进行缩小，生成表示第一属性的样本的第四结构（S4），具有比第一分辨率低的第二分辨率的样本的第四结构（S4）以形成样品的第四结构（S4）的样品。所述方法还包括基于样本的第三结构（S3），将表示第一属性的样本的第四结构（S4）扩展到第二结构（S2）中，所述上调包括将权重因子分配给基于样品的第三结构（S3）的样品的第四结构（S4）以及使用样本的第四结构（S4）的样本及其分配的权重因子来计算样本的第二结构（S2）的样本。本发明还涉及包括根据本发明的图像增强单元以及计算机程序产品的图像处理单元。

2. 发明授权

US08331711B2 Image enhancement 失效
标题翻译：图像增强
公开(公告)号：US08331711B2
公开(公告)日：2012-12-11
申请号：US12443728
申请日：2007-10-02
申请人： Om Prakash Gangwal , Eric Peter Funke , Christiaan Varekamp , Mickael Stephane Bernard George Bouvier
发明人： Om Prakash Gangwal , Eric Peter Funke , Christiaan Varekamp , Mickael Stephane Bernard George Bouvier
IPC分类号： G06K9/40 , G06K15/02
CPC分类号： G06T7/579 , H04N13/128 , H04N13/261
摘要： The present invention relates to an image enhancement unit and a method of enhancing a first structure (S1) of samples into a second structure (S2) of samples, the first and the second structure both representing a first property of a scene and having a first resolution, based on a third structure (S3) of samples representing a second property and having the first resolution, the first property and the second property respectively representing different properties of substantially the same scene. The method comprising generating a fourth structure (S4) of samples representing the first property, the fourth structure (S4) of samples having a second resolution lower than the first resolution, by down-scaling first samples of the first structure (S1) of samples to form the samples of the fourth structure (S4) of samples. The method further comprising up-scaling the fourth structure (S4) of samples representing the first property, into the second structure (S2) based on the third structure (S3) of samples, the up-scaling comprising assigning weight factors to respective samples of the fourth structure (S4) of samples based on samples of the third structure (S3) of samples; and computing samples of the second structure (S2) of samples using the samples of the fourth structure (S4) of samples and their respectively assigned weight factors. The invention further relates to an image-processing unit comprising an image enhancement unit according to the invention as well as to a computer program product.
摘要翻译：本发明涉及一种将样本的第一结构（S1）增强为样本的第二结构（S2）的图像增强单元和方法，所述第一和第二结构都表示场景的第一属性，并且具有第一分辨率，基于代表第二属性并具有第一分辨率的第三结构（S3），第一属性和第二属性分别表示基本上相同的场景的不同属性。该方法包括：通过对样本的第一结构（S1）的第一样本进行缩小，生成表示第一属性的样本的第四结构（S4），具有比第一分辨率低的第二分辨率的样本的第四结构（S4）以形成样品的第四结构（S4）的样品。所述方法还包括基于样本的第三结构（S3），将表示第一属性的样本的第四结构（S4）扩展到第二结构（S2）中，所述上调包括将权重因子分配给基于样品的第三结构（S3）的样品的第四结构（S4）以及使用样本的第四结构（S4）的样本及其分配的权重因子来计算样本的第二结构（S2）的样本。本发明还涉及包括根据本发明的图像增强单元以及计算机程序产品的图像处理单元。

3. 发明授权

US07653736B2 Data processing system having multiple processors and a communications means in a data processing system 有权
标题翻译：具有多个处理器的数据处理系统和数据处理系统中的通信装置
公开(公告)号：US07653736B2
公开(公告)日：2010-01-26
申请号：US10498596
申请日：2002-12-05
申请人： Josephus Theodorus Johannes Van Eijndhoven , Evert-Jan Daniël Pol , Martijn Johan Rutten , Pieter Van Der Wolf , Om Prakash Gangwal
发明人： Josephus Theodorus Johannes Van Eijndhoven , Evert-Jan Daniël Pol , Martijn Johan Rutten , Pieter Van Der Wolf , Om Prakash Gangwal
IPC分类号： G06F15/16
CPC分类号： G06F9/54
摘要： Aspects involve effectively separating communication hardware in a data processing system by introducing a communication device for each processor. By introducing this separation the processors can concentrate on performing their function-specific tasks, while the communication device provide the communication support for the respective processor. Accordingly, in certain embodiments, a data processing system is provided with a computation, a communication support and a communication network layer.
摘要翻译：方面涉及通过引入每个处理器的通信设备来有效地分离数据处理系统中的通信硬件。通过引入这种分离，处理器可以专注于执行其功能特定的任务，而通信设备为相应的处理器提供通信支持。因此，在某些实施例中，向数据处理系统提供计算，通信支持和通信网络层。

4. 发明申请

US20080267211A1 Integrated Circuit and Method for Time Slot Allocation 审中-公开
标题翻译：集成电路和时隙分配方法
公开(公告)号：US20080267211A1
公开(公告)日：2008-10-30
申请号：US11569979
申请日：2005-06-08
申请人： Om Prakash Gangwal , Andrei Radulescu , Kees Gerard Willem Goossens
发明人： Om Prakash Gangwal , Andrei Radulescu , Kees Gerard Willem Goossens
IPC分类号： H04L12/43 , H04J3/16
CPC分类号： H04Q11/04
摘要： An integrated circuit comprising a plurality of processing modules (M, S; IP) and a network (N) arranged for coupling said modules (M, S; IP) is provided. Said integrated circuit further comprises a plurality of network interfaces (NI) each being coupled between one of said processing modules (M, S; IP) and said network (N). Said network (N) comprises a plurality of routers (R) coupled via network links (L) to adjacent routers (R). Said processing modules (M, S; IP) communicate between each other over connections using connection paths (C1-C12) through the network (N), wherein each of said connection paths (C1-C12) employ at least one network link (L) for a required number of time slots. At least one time slot allocating unit (SA) is provided for allocating time slots to said network links (L) for determining unused time slots and for allocation the determined unused time slots to one or more of the connections using said network link in addition to its already allocated time slots.
摘要翻译：提供一种包括多个处理模块（M，S; IP）和布置用于耦合所述模块（M，S; IP）的网络（N）的集成电路。所述集成电路还包括多个网络接口（NI），每个网络接口（NI）耦合在所述处理模块（M，S; IP）和所述网络（N）中的一个之间。所述网络（N）包括经由网络链路（L）耦合到相邻路由器（R）的多个路由器（R）。所述处理模块（M，S; IP）通过使用通过网络（N）的连接路径（C 1 -C 12）的连接彼此通信，其中每个所述连接路径（C 1 -C 12）使用至少一个网络链路（L），用于所需数量的时隙。提供至少一个时隙分配单元（SA）用于向所述网络链路（L）分配时隙以确定未使用的时隙，并且还使用所述网络链路将确定的未使用的时隙分配给一个或多个连接，除了它已经分配了时隙。

5. 发明申请

US20120256906A1 SYSTEM AND METHOD TO RENDER 3D IMAGES FROM A 2D SOURCE 审中-公开
标题翻译：从2D源渲染3D图像的系统和方法
公开(公告)号：US20120256906A1
公开(公告)日：2012-10-11
申请号：US13250895
申请日：2011-09-30
申请人： Kevin Ross , Robertus Vogelaar , Om Prakash Gangwal , Johan Janssen , Haiyan He , Wim Michiels , Erwin Bellers
发明人： Kevin Ross , Robertus Vogelaar , Om Prakash Gangwal , Johan Janssen , Haiyan He , Wim Michiels , Erwin Bellers
IPC分类号： G06T15/04
CPC分类号： G06T15/205
摘要： A system and method to render 3D images from a 2D source are described. An embodiment of a method to render 3D images from a 2D source comprises the steps of providing a graphics rendering device to estimate depth of a 2D image; providing video or graphics textures and depth-maps to describe an object in a 3D scene; creating, in one embodiment, a single view angle and in another preferred embodiment at least two view angles of the 3D scene to represent an intraocular distance using the graphics rendering device; and presenting both of the at least two view angles on a display using the graphics rendering device and especially the commonly available 3D imaging technology of the graphics rendering device.
摘要翻译：描述从2D源渲染3D图像的系统和方法。从2D源渲染3D图像的方法的实施例包括以下步骤：提供图形渲染设备以估计2D图像的深度; 提供视频或图形纹理和深度图以描述3D场景中的对象; 在一个实施例中，在一个实施例中创建单个视角，并且在另一个优选实施例中，使用图形渲染装置来3D 3D场景的至少两个视角来表示眼内距离; 以及使用所述图形绘制设备，特别是所述图形渲染设备的通常可用的3D成像技术，在显示器上呈现所述至少两个视角。

6. 发明授权

US07725681B2 Parallel processing array 有权
标题翻译：并行处理阵列
公开(公告)号：US07725681B2
公开(公告)日：2010-05-25
申请号：US10568013
申请日：2004-08-03
申请人： Om Prakash Gangwal , Anteneh Alemu Abbo , Richard Petrus Kleihorst
发明人： Om Prakash Gangwal , Anteneh Alemu Abbo , Richard Petrus Kleihorst
IPC分类号： G06F15/80
CPC分类号： G06F15/8007 , G06F9/355
摘要： A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag register (FLAG) (9). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element (1) further comprises a storage element (SE) (11), which supports the processing of local customized (i.e. data dependent) processing in the processing element (1), such as lookup table operations and the storing local coefficient data.
摘要翻译：构成诸如SIMD的并行处理阵列的一部分的处理元件（1）包括算术逻辑单元（ALU）（3），多路复用器（MUX）（5），累加器（ACCU）（7）和标志寄存器 FLAG）（9）。 ALU被配置为对由处理阵列中的所有处理元件接收的公共指令进行操作。处理元件（1）还包括存储元件（SE）（11），其支持处理元件（1）中的本地定制（即数据相关）处理的处理，诸如查找表操作和存储局部系数数据。

7. 发明申请

US20090122703A1 Electronic Device and Method for Flow Control 审中-公开
标题翻译：电子装置及流量控制方法
公开(公告)号：US20090122703A1
公开(公告)日：2009-05-14
申请号：US11911034
申请日：2006-04-03
申请人： Om Prakash Gangwal , Andrei Radulescu
发明人： Om Prakash Gangwal , Andrei Radulescu
IPC分类号： H04J1/16
CPC分类号： H04L47/10 , H04L47/29 , H04L47/35 , H04L47/39
摘要： An electronic device is provided comprising a plurality of processing units (IP; MIP, SIP); an interconnect means (NOC) for coupling the plurality of processing units (IP; MIP, SIP); and a plurality of interia.ee means (NI; MNI, SNI) arranged between one of the processing units (IP; MIP, SIP) and the interconnect means (NOC), for enabling a communication between the processing units (IP; MIP, SIP) and the interconnect means. The communication between the processing units (IP; MIP, SIP) is a packet-based communication via the interface means (NI; MNI, SNI) and the interconnect means (NOC). Each packet first comprises a first header (H) followed by a pay load (P). Said interface means comprise (NI; MNI, SNI) a flow control means (FCM) for controlling the communication flow between two processing units (IP; MIP, SIP) based on flow control credit information (C), for inserting the first header (H) in each packet, and for additionally inserting a second header (H) into a packet according to an amount of required flow control credit information (C).
摘要翻译：提供了包括多个处理单元（IP; MIP，SIP）的电子设备; 用于耦合所述多个处理单元（IP; MIP，SIP）的互连装置（NOC）; 以及布置在所述处理单元（IP; MIP，SIP）之一和所述互连装置（NOC）之间的多个干预装置（NI; MNI，SNI），用于使得所述处理单元（IP; MIP， SIP）和互连装置。处理单元（IP; MIP，SIP）之间的通信是经由接口装置（NI; MNI，SNI）和互连装置（NOC）的基于分组的通信。每个分组首先包括第一报头（H），随后是付费负载（P）。所述接口装置包括（NI; MNI，SNI）流控制装置（FCM），用于基于流控制信用信息（C）控制两个处理单元（IP; MIP，SIP）之间的通信流，用于插入第一报头 H），并且用于根据所需的流量控制信用信息（C）的量附加地将第二报头（H）插入到分组中。

8. 发明授权

US07594046B2 Data processing in which concurrently executed processes communicate via a FIFO buffer 有权
标题翻译：数据处理，其中并发执行的处理通过FIFO缓冲器进行通信
公开(公告)号：US07594046B2
公开(公告)日：2009-09-22
申请号：US10552778
申请日：2004-04-08
申请人： Om Prakash Gangwal
发明人： Om Prakash Gangwal
IPC分类号： G06F3/00 , G06F5/00 , G06F9/00 , G06F9/44 , G06F13/00 , G06K9/00 , H03K19/00
CPC分类号： G06F5/10
摘要： A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream. A first-in first-out buffer passes data from the stream between the data producing process and the data consuming process. The buffer comprises buffer memory, the buffer writes data-items from the stream in circular fashion into the buffer memory. A consuming process interface is arranged to process a command for making a data grain from the stream available to the data consuming process. The interface responds to the command by testing whether addresses of data within the grain to which access has to be gained wrap around in the circular FIFO buffer. The interface copies the grain from the FIFO buffer to the auxiliary memory region, on condition that the addresses wrap around, so that the wrap around is eliminated in the copied grain, The interface returns an indication to the consuming process to read the grain from the FIFO buffer when the addresses do not wrap around inside the grain, or an indication to read from the auxiliary memory region, when the addresses wrap around.
摘要翻译：处理电路执行数据产生处理和数据消耗处理。数据产生过程产生数据流，数据消耗过程在生成流时同时消耗数据流。先进先出的缓冲区在数据产生过程和数据消耗过程之间传送数据流。缓冲器包括缓冲存储器，缓冲器将数据流以循环方式写入缓冲存储器。消耗过程接口被布置为处理用于从可用于数据消耗过程的流中产生数据粒度的命令。接口通过测试在循环FIFO缓冲区内是否需要获取访问的粒度内的数据地址来回应命令。界面将边界从FIFO缓冲区复制到辅助存储器区域，条件是地址环绕，从而在复制的纹理中消除了环绕。接口返回消耗过程的指示，以从当地址环绕时，地址不会包围在颗粒内的FIFO缓冲区或从辅助存储器区域读取的指示。

9. 发明申请

US20070133399A1 Data processing in which concurrently executed processes communicate via a fifo buffer 有权
标题翻译：数据处理，其中并发执行的进程通过fifo缓冲区进行通信
公开(公告)号：US20070133399A1
公开(公告)日：2007-06-14
申请号：US10552778
申请日：2004-04-08
申请人： Om Prakash Gangwal
发明人： Om Prakash Gangwal
IPC分类号： H04L12/26 , H04L12/50
CPC分类号： G06F5/10
摘要： A processing circuit executes a data producing process and a data consuming process. The data producing process produces a stream of data, the data consuming process consumes the stream of data concurrently with production of the stream. A first-in first-out buffer passes data from the stream between the data producing process and the data consuming process. The buffer comprises buffer memory, the buffer writes data-items from the stream in circular fashion into the buffer memory. A consuming process interface is arranged to process a command for making a data grain from the stream available to the data consuming process. The interface responds to the command by testing whether addresses of data within the grain to which access has to be gained wrap around in the circular FIFO buffer. The interface copies the grain from the FIFO buffer to the auxiliary memory region, on condition that the addresses wrap around, so that the wrap around is eliminated in the copied grain, The interface returns an indication to the consuming process to read the grain from the FIFO buffer when the addresses do not wrap around inside the grain, or an indication to read from the auxiliary memory region, when the addresses wrap around.
摘要翻译：处理电路执行数据产生处理和数据消耗处理。数据产生过程产生数据流，数据消耗过程在生成流时同时消耗数据流。先进先出的缓冲区在数据产生过程和数据消耗过程之间传送数据流。缓冲器包括缓冲存储器，缓冲器将数据流以循环方式写入缓冲存储器。消耗过程接口被布置为处理用于从可用于数据消耗过程的流中产生数据粒度的命令。接口通过测试在循环FIFO缓冲区内是否需要获取访问的粒度内的数据地址来回应命令。界面将边界从FIFO缓冲区复制到辅助存储器区域，条件是地址环绕，从而在复制的纹理中消除了环绕。接口返回消耗过程的指示，以从当地址环绕时，地址不会包围在颗粒内的FIFO缓冲区或从辅助存储器区域读取的指示。

10. 发明授权

US07706377B2 Video processing circuit and method of video processing 失效
标题翻译：视频处理电路及视频处理方法
公开(公告)号：US07706377B2
公开(公告)日：2010-04-27
申请号：US10591390
申请日：2005-02-25
申请人： Pieter Van Der Wolf , Abraham Karel Riemens , Om Prakash Gangwal
发明人： Pieter Van Der Wolf , Abraham Karel Riemens , Om Prakash Gangwal
IPC分类号： H04L12/28
CPC分类号： H04N19/85 , H04N19/159 , H04N19/423 , H04N19/44 , H04N19/61
摘要： Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106). The second video processing function reads frame data from first and second ones of the frames selectively from the first and second buffer memory (12, 106) respectively. The second ones of the frames occur in the same temporal order in both the input and output sequence. The first ones of the frames contain at least all particular frames whose position relative to the second ones of the frames in the output sequence differs from the position of the particular frames relative to the second ones of the frames in the input sequence.
摘要翻译：诸如包括MPEG解码后续后处理的视频流处理涉及使用信号处理电路（102,106）来执行第一和第二视频流处理功能。第一视频流处理功能在时间有序的输出帧序列中产生连续视频帧的帧数据。第二视频流处理功能使用与输出序列不同的帧的有序输入序列中的帧数据，例如因为需要稍后的P帧来解码B帧。帧数据在第一和第二视频处理功能的应用与帧数据之间被缓冲。第一和第二。使用缓冲存储器（12,106）。第一缓冲存储器（12）经由诸如外部IC端子之类的共享通道（15）耦合到信号处理电路，但处理电路不使用可共享通道（15）访问第二缓冲存储器（106）。第二视频处理功能分别从第一和第二缓冲存储器（12,106）中选择性地从第一和第二帧中读取帧数据。帧中的第二帧在输入和输出序列中以相同的时间顺序发生。帧中的第一帧包含至少所有特定帧，其相对于输出序列中的第二帧的位置与特定帧相对于输入序列中的第二帧的位置不同。

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