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1. 发明授权

US07696784B1 Programmable logic device with multiple slice types 有权
标题翻译：具有多种切片类型的可编程逻辑器件
公开(公告)号：US07696784B1
公开(公告)日：2010-04-13
申请号：US12105959
申请日：2008-04-18
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment, a programmable logic device includes a plurality of programmable logic blocks and a plurality of slices within each of the programmable logic blocks. At least one programmable logic blocks includes a first slice not adapted to provide register functionality or RAM functionality, a second slice adapted to provide register functionality but not RAM functionality, and a third slice adapted to provide register functionality and RAM functionality. Control logic within the programmable logic block is adapted to provide control signals at the programmable block level and at the slice level.
摘要翻译：在一个实施例中，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个片。至少一个可编程逻辑块包括不适于提供寄存器功能或RAM功能的第一片，适于提供寄存器功能而不是RAM功能的第二片，以及适于提供寄存器功能和RAM功能的第三片。可编程逻辑块内的控制逻辑适于在可编程块级和限幅级提供控制信号。

2. 发明授权

US07592834B1 Logic block control architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的逻辑块控制架构
公开(公告)号：US07592834B1
公开(公告)日：2009-09-22
申请号：US12164265
申请日：2008-06-30
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment of the invention, a programmable logic device comprises configuration memory adapted to store configuration data and a plurality of programmable logic blocks. At least one programmable logic block includes a plurality of dual-slice logic blocks, each dual-slice logic block including first and second slices, each slice including at least two lookup tables (LUTs) and a register. The programmable logic block further includes control logic adapted for selecting control signals separately at a programmable block level, a dual-slice block level, and a register level, the control logic responsive to configuration data stored within the configuration memory.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件包括适于存储配置数据和多个可编程逻辑块的配置存储器。至少一个可编程逻辑块包括多个双切片逻辑块，每个双切片逻辑块包括第一和第二切片，每个切片包括至少两个查找表（LUT）和寄存器。可编程逻辑块还包括适于在可编程块级别，双切片块级别和寄存器级别分别选择控制信号的控制逻辑，该控制逻辑响应于存储在配置存储器内的配置数据。

3. 发明授权

US07605606B1 Area efficient routing architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的区域高效路由架构
公开(公告)号：US07605606B1
公开(公告)日：2009-10-20
申请号：US11498646
申请日：2006-08-03
申请人： Ming H. Ding , Sajitha Wijesuriya , Jun Zhao , Om P. Agrawal , Barry Britton , Xiaojie He
发明人： Ming H. Ding , Sajitha Wijesuriya , Jun Zhao , Om P. Agrawal , Barry Britton , Xiaojie He
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.
摘要翻译：系统和方法为可编程逻辑块提供可编程逻辑块架构和路由架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个逻辑块片。第一路由电路在可编程逻辑器件内为相应的可编程逻辑块提供全局信号路由。第一输入路由电路从第一路由电路接收信号并将信号路由到相应的可编程逻辑块内的逻辑块片段。

4. 发明授权

US07378872B1 Programmable logic device architecture with multiple slice types 有权
标题翻译：具有多种切片类型的可编程逻辑器件架构
公开(公告)号：US07378872B1
公开(公告)日：2008-05-27
申请号：US11445620
申请日：2006-06-02
申请人： Om P. Agrawal , Barry Britton , Xiaojie He , Sajitha Wijesuriya , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Barry Britton , Xiaojie He , Sajitha Wijesuriya , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块，其中至少一个可编程逻辑块具有至少第一，第二和第三逻辑块片不同的逻辑块片类型。

5. 发明授权

US07675321B1 Dual-slice architectures for programmable logic devices 有权
标题翻译：可编程逻辑器件的双切片架构
公开(公告)号：US07675321B1
公开(公告)日：2010-03-09
申请号：US12409757
申请日：2009-03-24
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H01L25/00 , G06F7/38
CPC分类号： H03K19/17736 , H03K19/17728
摘要： In one embodiment of the invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within a programmable logic block. A dual-slice logic block includes a first slice including at least two lookup tables (LUTs); a second slice including at least two LUTs; and a routing circuit coupled to each of the LUTs within the first and second slices. The routing circuit is adapted to share outputs of the dual-slice logic block among the LUTs. In another embodiment of the invention, the dual-slice logic block includes a second routing circuit coupled to each of the LUTs within the first and second slices. The second routing circuit is adapted to share inputs of the dual-slice logic block among the LUTs.
摘要翻译：在本发明的一个实施例中，可编程逻辑器件包括可编程逻辑块内的多个可编程逻辑块和多个双片逻辑块。双切片逻辑块包括包括至少两个查找表（LUT）的第一切片; 包括至少两个LUT的第二片; 以及耦合到第一和第二切片内的每个LUT的路由电路。路由电路适于在LUT之间共享双层逻辑块的输出。在本发明的另一个实施例中，双切片逻辑块包括耦合到第一和第二切片内的每个LUT的第二路由电路。第二路由电路适于在LUT之间共享双层逻辑块的输入。

6. 发明授权

US07397276B1 Logic block control architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的逻辑块控制架构
公开(公告)号：US07397276B1
公开(公告)日：2008-07-08
申请号：US11446351
申请日：2006-06-02
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks, with each of the logic block slices having at least a first and a second slice each having at least a first lookup table. At least one of the programmable logic blocks includes at least a first logic block slice, a second logic block slice, and a third logic block slice, with the first logic block slice being a logic block slice type different from the second logic block slice, and the third logic block slice being a logic block slice type different from the first and second logic block slices. Control logic provides at a programmable logic block level bundled and/or unbundled control signals at a logic block slice level for at least two of the logic block slices.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个逻辑块片，每个逻辑块片段具有至少一个第一片和第二片，每片具有至少第一查找表。至少一个可编程逻辑块至少包括第一逻辑块片段，第二逻辑块片段和第三逻辑块片段，其中第一逻辑块片段是不同于第二逻辑块片段的逻辑块片段类型，并且第三逻辑块片是不同于第一和第二逻辑块片段的逻辑块片段类型。逻辑块片段中的至少两个逻辑块片级的控制逻辑在逻辑块片级提供捆绑和/或非捆绑控制信号的可编程逻辑块级。

7. 发明授权

US07385417B1 Dual slice architectures for programmable logic devices 有权
标题翻译：可编程逻辑器件的双切片架构
公开(公告)号：US07385417B1
公开(公告)日：2008-06-10
申请号：US11446542
申请日：2006-06-02
申请人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Xiaojie He , Sajitha Wijesuriya , Barry Britton , Ming H. Ding , Jun Zhao
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide dual slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of dual-slice logic blocks within each of the programmable logic blocks, wherein each dual-slice logic block includes a first and a second slice each having at least a first lookup table, with a first one of the dual-slice logic blocks of a logic block slice type different from a second one of the dual-slice logic blocks, and a third one of the dual-slice logic blocks of a logic block slice type different from the first and second dual-slice logic blocks.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供双切片架构和可编程逻辑块结构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个双层逻辑块，其中每个双层逻辑块包括第一和第二切片，其每个具有至少第一查找表，其中第一个双逻辑块逻辑块的逻辑块片类型与第二个双片逻辑块不同，与第一和第二双层逻辑块不同的逻辑块片类型的双片逻辑块。

8. 发明授权

US09648474B2 Efficiently transmitting bulk data over a mobile network 有权
公开(公告)号：US09648474B2
公开(公告)日：2017-05-09
申请号：US14868299
申请日：2015-09-28
申请人： Om P. Agrawal , Anita Agrawal
发明人： Om P. Agrawal , Anita Agrawal
IPC分类号： H04W4/14 , H04L12/58
CPC分类号： H04W4/14 , H04L51/30 , H04L51/34 , H04L51/36 , H04L51/38
摘要： A method for efficiently transmitting bulk data over a mobile network using predetermined fillable templates may include correlating records in a database with an input field of a predetermined fillable template and a report field of a predetermined report. The template may be provided to a user by way of a downloadable and executable mobile application. The method may include receiving discrete SMS messages populated into the input fields of the template by a user of a mobile device upon which the mobile application has been installed. The method may include associating each received SMS message with a corresponding report field of the predetermined report according. The method may include populating the corresponding report field of the predetermined report with report information based on the received SMS message. The method may also include providing the predetermined report to a computing device associated with a second user.

9. 发明授权

US07787326B1 Programmable logic device with a multi-data rate SDRAM interface 有权
标题翻译：具有多数据速率SDRAM接口的可编程逻辑器件
公开(公告)号：US07787326B1
公开(公告)日：2010-08-31
申请号：US12019526
申请日：2008-01-24
申请人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
发明人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
IPC分类号： G11C8/18
CPC分类号： G06F13/4243
摘要： Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.
摘要翻译：在可编程逻辑器件中，诸如DDR SDRAM接口的多数据速率SDRAM接口在一个实施例中包括DQS时钟树，从延迟电路和延迟锁定环（DLL）。从延迟电路适于相对于数据相位移位DQS信号的相位，以向DQS时钟树提供相移DQS信号，并且该DLL适于控制从延迟电路。该DLL包括延迟线，其包括从延迟电路的多个实例和DQS时钟树的多个传真机。

10. 发明授权

US07342838B1 Programmable logic device with a double data rate SDRAM interface 有权
标题翻译：具有双数据速率SDRAM接口的可编程逻辑器件
公开(公告)号：US07342838B1
公开(公告)日：2008-03-11
申请号：US11165853
申请日：2005-06-24
申请人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
发明人： Brad Sharpe-Geisler , Om P. Agrawal , Kiet Truong , Giap Tran , Bai Nguyen
IPC分类号： G11C7/00
CPC分类号： G06F13/4243
摘要： Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.
摘要翻译：在可编程逻辑器件（PLD）中，提供用于DDR SDRAM的DDR SDRAM接口，DDR SDRAM在DQS信号的上升沿和下降沿向PLD提供数据，该接口包括：适于捕获数据的第一寄存器与DQS信号的下降沿相关联; 第二寄存器，其适于捕获与所述DQS信号的上升沿相关联的数据; 以及时钟沿选择逻辑电路，其耦合到第一和第二寄存器的时钟输入，并且适于在内部PLD时钟的上升沿或下降时钟沿之间进行选择，以对第一和第二寄存器进行时钟，从而将捕获的数据传输到核心逻辑 PLD，根据内部PLD时钟和DQS信号之间的相位关系选择时钟沿。

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