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1. 发明授权

US5141884A Isolation method of semiconductor device 失效
标题翻译：半导体器件分离方法
公开(公告)号：US5141884A
公开(公告)日：1992-08-25
申请号：US612559
申请日：1990-11-13
申请人： Oh H. Kwon , Dong J. Bae
发明人： Oh H. Kwon , Dong J. Bae
IPC分类号： H01L29/78 , H01L21/316 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L29/66575 , H01L21/76227 , Y10S438/975
摘要： An isolation method of semiconductor devices comprises the steps of forming a multilayer, defining both active and isolating regions, forming a channel stopper, removing the multilayer on a nitride layer to form a capping oxide layer, removing the multilayer on the nitride layer and a polysilicon layer to form an isolation layer, forming spacers at sidewalls of the isolation region, forming a gate oxide layer and a gate oxide electrode, and forming a second conductive diffusion regions, wherein the CVD process and photolithography methods are applied in formation of the isolating layer not to result in the bird's beak and dislocation caused by stress and the channel stopper is formed by ion-implantation of impurity without its diffusion not to contact with the isolating layer by the spacers on the sidewalls thereof in its diffusion region which is formed by the ion-implantation. Therefore, according to the present invention, the limit of the isolation can be extended into a sub-micron range so as to prevent the narrow channel effect and increase the breakdown voltage.
摘要翻译：半导体器件的隔离方法包括以下步骤：形成多层，限定有源区和隔离区，形成通道阻挡层，去除氮化物层上的多层以形成覆盖氧化物层，去除氮化物层上的多层和多晶硅层以形成隔离层，在隔离区的侧壁形成间隔物，形成栅极氧化层和栅极氧化物电极，以及形成第二导电扩散区，其中CVD法和光刻法用于形成隔离层不会导致鸟的喙和应力引起的位错，并且通过离子注入杂质形成通道阻挡物，而不会使其扩散而不与其隔离层通过其侧壁上的间隔物在其扩散区域中形成，该扩散区由离子注入。因此，根据本发明，隔离的极限可以扩展到亚微米范围，以防止窄通道效应并增加击穿电压。

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