专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10884472B2 Current compensation during dynamic voltage and frequency scaling transitions 有权
公开(公告)号：US10884472B2
公开(公告)日：2021-01-05
申请号：US15965765
申请日：2018-04-27
申请人： Oracle International Corporation
发明人： Yufei Qian , Yifan YangGong , Sebastian Turullols
IPC分类号： G06F1/3206 , G06F1/324
摘要： A method for adjusting operation parameters of a computer system based on power consumption of the computer system is disclosed. During a power state transition of the computer system, a voltage level of a power supply signal may be sampled at a plurality of time points to generate a multiple voltage level samples. A voltage level of a selected one of the multiple voltage level samples may be adjusted using a particular coefficient of multiple coefficients to generate an updated voltage level sample. A power consumption of the computer system may be determined using the updated voltage level sample, and based on the power consumption, at least one operation parameter of the computer system may be adjusted.

2. 发明授权

US10656700B2 Power management in an integrated circuit 有权
公开(公告)号：US10656700B2
公开(公告)日：2020-05-19
申请号：US15645528
申请日：2017-07-10
申请人： Oracle International Corporation
发明人： Yifan YangGong , Sebastian Turullols
IPC分类号： G06F1/324 , G06F1/3287 , G06F1/3296 , G06F1/3206 , G06F1/20
摘要： A power management controller is disclosed. Broadly speaking, the controller may, in response to detecting a timing signal, determine a total power consumption for a plurality of processor clusters, each of which includes a plurality of processor cores. The controller may determine a performance metric using the total power consumption and compare the performance metric to a limit. Based on a result of the comparison, the controller may select a new power state for at least one of the processor clusters.

3. 发明申请

US20190339137A1 ADAPTIVE METHOD FOR CALIBRATING MULTIPLE TEMPERATURE SENSORS ON A SINGLE SEMICONDUCTOR DIE 审中-公开
公开(公告)号：US20190339137A1
公开(公告)日：2019-11-07
申请号：US16459464
申请日：2019-07-01
申请人： Oracle International Corporation
发明人： Venkatram Krishnaswamy , Sebastian Turullols
IPC分类号： G01K15/00
摘要： A system is disclosed, including an interface to a DUT and a testing apparatus. The DUT includes a first plurality of temperature sensing circuits. The testing apparatus may store a plurality of control values. Each control value may depend on at least two calibration values of corresponding temperature sensing circuits of a second plurality of temperature sensing circuits. The testing apparatus may generate a plurality of calibration values for the DUT. Each calibration value corresponds to one of the first plurality of temperature sensing circuits. The testing apparatus may determine a plurality of test values for the DUT. The testing apparatus may calculate a probability value, and repeat generation of the plurality of calibration values upon determining that the probability value is less than a predetermined threshold value. The probability value corresponds to a likelihood that the plurality of calibration values is accurate.

4. 发明授权

US10296063B2 Integrated circuit current metering using voltage variation detection circuit 有权
公开(公告)号：US10296063B2
公开(公告)日：2019-05-21
申请号：US15474635
申请日：2017-03-30
申请人： Oracle International Corporation
发明人： Yifan YangGong , Sebastian Turullols , Vijay Srinivasan
IPC分类号： G06F1/324 , G06F1/3206 , G06F1/3296
摘要： An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

5. 发明申请

US20180284867A1 INTEGRATED CIRCUIT CURRENT METERING USING VOLTAGE VARIATION DETECTION CIRCUIT 审中-公开
公开(公告)号：US20180284867A1
公开(公告)日：2018-10-04
申请号：US15474635
申请日：2017-03-30
申请人： Oracle International Corporation
发明人： Yifan YangGong , Sebastian Turullols , Vijay Srinivasan
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296
摘要： An apparatus is disclosed, including a monitoring circuit, a translation circuit, a first filter circuit, a second filter circuit, and an interface. The monitoring circuit may be configured to receive a plurality of code values indicative of a voltage level of a power supply signal. The translation circuit may be configured to translate a particular code value to a corresponding voltage value of a plurality of voltage values. The first filter circuit may be configured to filter one or more of the plurality of voltage values to generate a plurality of filtered voltage values. The second filter circuit may be configured to generate a plurality of current values using one or more of the plurality of filtered voltage values and based on an impulse response of the power supply signal. The interface may be configured to send one or more of the plurality of current values to a functional circuit.

6. 发明授权

US09689917B2 Digital voltage droop monitor with clock jitter adjustment 有权
公开(公告)号：US09689917B2
公开(公告)日：2017-06-27
申请号：US14691352
申请日：2015-04-20
申请人： Oracle International Corporation
发明人： Sebastian Turullols , Vijay Srinivasan , Changku Hwang
IPC分类号： G06F1/28 , G01R31/317 , G06F1/32 , H03K3/037 , H03K5/159 , G01R31/30 , H03K5/133
CPC分类号： G01R31/31725 , G01R31/3004 , G01R31/31937 , G06F1/3206 , G06F1/3296 , H03K3/037 , H03K5/133 , H03K5/159
摘要： Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit may include a clock jitter monitor circuit configured with a constant supply voltage. This clock jitter monitor is configured to measure the clock jitter that is experienced by the digital voltage monitor circuit and, when compared to measured voltage captured by the circuit, may be used to calibrate or otherwise correct the readings provided by the digital voltage monitor circuit.

7. 发明申请

US20170132344A1 MICRO-BENCHMARK ANALYSIS OPTIMIZATION FOR MICROPROCESSOR DESIGNS 审中-公开
公开(公告)号：US20170132344A1
公开(公告)日：2017-05-11
申请号：US15291459
申请日：2016-10-12
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： Haowei Zhang , Xiaoying Shen , Sebastian Turullols
IPC分类号： G06F17/50 , G06F17/16 , G06F17/11
CPC分类号： G06F17/5036 , G06F17/11 , G06F17/16 , G06F17/5009 , G06F17/5031 , G06F17/5081 , G06F2217/84 , G06F2217/86
摘要： Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.

8. 发明授权

US09599645B2 High speed clock cycle rate digital voltage monitor with triggered tracing for integrated circuits 有权
公开(公告)号：US09599645B2
公开(公告)日：2017-03-21
申请号：US13903445
申请日：2013-05-28
申请人： Oracle International Corporation
发明人： Sebastian Turullols
IPC分类号： G01R31/28 , G01R29/26 , G01R19/25 , G01R31/317
CPC分类号： G01R19/2503 , G01R31/31721
摘要： Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilizes a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. The digitized samples are routed to either an on-die memory structure for later analysis or are transmitted to one or more pins of a chip for capture and analysis by an external analyzer.

9. 发明授权

US09483603B2 Micro-benchmark analysis optimization for microprocessor designs 有权
标题翻译：微处理器设计的微基准分析优化
公开(公告)号：US09483603B2
公开(公告)日：2016-11-01
申请号：US14293763
申请日：2014-06-02
申请人： Oracle International Corporation
发明人： Haowei Zhang , Xiaoying Shen , Sebastian Turullols
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/11 , G06F17/16 , G06F17/5009 , G06F17/5031 , G06F17/5081 , G06F2217/84 , G06F2217/86
摘要： Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design.
摘要翻译：实施例包括用于优化微处理器设计的微基准分析的系统和方法。例如，实施例寻求生成一组微基准和相关联的加权因子，其可以用于以对于细粒度（例如，RTL）模拟）有效地定义加权聚合工作负载条件，其方式是足够的代理预测商业工作量情况。微型基准测试套件可以比商业工作量更高效地模拟，因此使用微型基准套件作为商业工作负载的代理可以提供许多好处，包括更有效的迭代设计。

10. 发明申请

US20160033576A1 HIGH SENSITIVITY DIGITAL VOLTAGE DROOP MONITOR FOR INTEGRATED CIRCUITS 有权
标题翻译：用于集成电路的高灵敏度数字电压监视器
公开(公告)号：US20160033576A1
公开(公告)日：2016-02-04
申请号：US14691332
申请日：2015-04-20
申请人： Oracle International Corporation
发明人： Sebastian Turullols , Vijay Srinivasan , Changku Hwang
IPC分类号： G01R31/317 , G01R19/25
CPC分类号： G01R31/31725 , G01R31/3004 , G01R31/31937 , G06F1/3206 , G06F1/3296 , H03K3/037 , H03K5/133 , H03K5/159
摘要： Implementations of the present disclosure involve a system and/or method for measuring on-die voltage levels of an integrated circuit through a digital sampling circuit. In particular, the system and/or method utilize a delay line based analog-to-digital sampling circuit that produces a voltage reading over time, such as at every high frequency clock cycle. In one embodiment, the digital sampling circuit or digital voltage monitor circuit includes a coarse delay component or circuit that further delays the propagation of a clock signal through the delay line. The coarse delay circuit may be programmed to delay the propagation of the signal through the delay line in such a manner as to allow for multiple edges of a clock or test signal to travel simultaneously down the delay line and increase the sensitivity of the circuit. Additional sensitivity of the digital voltage monitor circuit may also be obtained through selection of the types of components that comprise the circuit and a clock jitter monitor circuit configured with a constant supply voltage.
摘要翻译：本公开的实现涉及用于通过数字采样电路测量集成电路的片上电压电平的系统和/或方法。特别地，系统和/或方法利用基于延迟线的模数 - 数字采样电路，其产生随时间的电压读数，例如在每个高频时钟周期。在一个实施例中，数字采样电路或数字电压监视电路包括粗略延迟分量或电路，其进一步延迟时钟信号通过延迟线的传播。粗延迟电路可以被编程为延迟信号通过延迟线的传播，以便允许时钟或测试信号的多个边沿同时沿着延迟线行进并且增加电路的灵敏度。也可以通过选择构成电路的部件的类型和配置有恒定电源电压的时钟抖动监视电路来获得数字电压监视器电路的附加灵敏度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式