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1. 发明授权

US11886980B2 Neural network accelerator using logarithmic-based arithmetic 有权
公开(公告)号：US11886980B2
公开(公告)日：2024-01-30
申请号：US16549683
申请日：2019-08-23
申请人： NVIDIA Corporation
发明人： William James Dally , Rangharajan Venkatesan , Brucek Kurdo Khailany
IPC分类号： G06N3/06 , G06N3/063 , G06F17/16 , G06F7/483
CPC分类号： G06N3/063 , G06F7/4833 , G06F17/16
摘要： Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

2. 发明申请

US20220004864A1 PREVENTING GLITCH PROPAGATION 有权
公开(公告)号：US20220004864A1
公开(公告)日：2022-01-06
申请号：US16919375
申请日：2020-07-02
申请人： NVIDIA Corporation
发明人： William James Dally
IPC分类号： G06N3/08 , H03K3/037 , H03K5/01 , H03K19/003 , G06N3/063 , G06N3/04 , G06F1/12
摘要： When a signal glitches, logic receiving the signal may change in response, thereby charging and/or discharging nodes within the logic and dissipating power. Providing a glitch-free signal may reduce the number of times the nodes are charged and/or discharged, thereby reducing the power dissipation. A technique for eliminating glitches in a signal is to insert a storage element that samples the signal after it is done changing to produce a glitch-free output signal. The storage element is enabled by a “ready” signal having a delay that matches the delay of circuitry generating the signal. The technique prevents the output signal from changing until the final value of the signal is achieved. The output signal changes only once, typically reducing the number of times nodes in the logic receiving the signal are charged and/or discharged so that power dissipation is also reduced.

3. 发明申请

US20210056446A1 INFERENCE ACCELERATOR USING LOGARITHMIC-BASED ARITHMETIC 有权
公开(公告)号：US20210056446A1
公开(公告)日：2021-02-25
申请号：US16750823
申请日：2020-01-23
申请人： NVIDIA Corporation
发明人： William James Dally , Rangharajan Venkatesan , Brucek Kurdo Khailany
IPC分类号： G06N5/04
摘要： Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

4. 发明授权

US11977766B2 Hierarchical network for stacked memory system 有权
公开(公告)号：US11977766B2
公开(公告)日：2024-05-07
申请号：US17683292
申请日：2022-02-28
申请人： NVIDIA Corporation
发明人： William James Dally , Carl Thomas Gray , Stephen W. Keckler , James Michael O'Connor
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

5. 发明公开

US20230385232A1 MAPPING LOGICAL AND PHYSICAL PROCESSORS AND LOGICAL AND PHYSICAL MEMORY 审中-公开
公开(公告)号：US20230385232A1
公开(公告)日：2023-11-30
申请号：US18227241
申请日：2023-07-27
申请人： NVIDIA Corporation
发明人： William James Dally
IPC分类号： G06F15/80 , G06F12/06
CPC分类号： G06F15/80 , G06F12/0646 , G06F2212/7201
摘要： A mapping may be made between an array of physical processors and an array of functional logical processors. Also, a mapping may be made between logical memory channels (associated with the logical processors) and functional physical memory channels (associated with the physical processors). These mappings may be stored within one or more tables, which may then be used to bypass faulty processors and memory channels when implementing memory accesses, while optimizing locality (e.g., by minimizing the proximity of memory channels to processors).

6. 发明申请

US20210048992A1 PROCESSOR FOR PERFORMING DYNAMIC PROGRAMMING ACCORDING TO AN INSTRUCTION, AND A METHOD FOR CONFIGURING A PROCESSOR FOR DYNAMIC PROGRAMMING VIA AN INSTRUCTION 有权
公开(公告)号：US20210048992A1
公开(公告)日：2021-02-18
申请号：US16811068
申请日：2020-03-06
申请人： Nvidia Corporation
发明人： William James Dally
IPC分类号： G06F8/41 , G06T1/20 , G06F9/50
摘要： The disclosure provides processors that are configured to perform dynamic programming according to an instruction, a method for configuring a processor for dynamic programming according to an instruction and a method of computing a modified Smith Waterman algorithm employing an instruction for configuring a parallel processing unit. In one example, the method for configuring includes: (1) receiving, by execution cores of the processor, an instruction that directs the execution cores to compute a set of recurrence equations employing a matrix, (2) configuring the execution cores, according to the set of recurrence equations, to compute states for elements of the matrix, and (3) storing the computed states for current elements of the matrix in registers of the execution cores, wherein the computed states are determined based on the set of recurrence equations and input data.

7. 发明申请

US20140232368A1 ELECTRIC POWER CONVERSION WITH ASSYMETRIC PHASE RESPONSE 审中-公开
标题翻译：电力转换与相位相位响应
公开(公告)号：US20140232368A1
公开(公告)日：2014-08-21
申请号：US13770656
申请日：2013-02-19
申请人： NVIDIA CORPORATION
发明人： William James Dally
IPC分类号： H02M3/155
CPC分类号： H02M3/155 , H02M3/1584 , H02M2003/1566
摘要： The disclosure is directed to a multi-phase electric power conversion device coupled between a power source and a load. The device includes a first regulator phase and a second regulator phase arranged in parallel, so that a first phase current and a second phase current are controllably provided in parallel to satisfy the current demand requirements of the load. Each phase current is based on current generated in an energy storage device within the respective phase. The regulator phases are asymmetric in that the energy storage device of the second regulator phase is configured so that its current can be varied more rapidly than the current in the energy storage device of the first regulator phase.
摘要翻译：本公开涉及耦合在电源和负载之间的多相电力转换装置。该装置包括并联布置的第一调节器相和第二调节器相，使得可并联地可控地提供第一相电流和第二相电流，以满足负载的当前需求要求。每相电流基于在相应相位内的能量存储装置中产生的电流。调节器相位是不对称的，因为第二调节器相的能量存储装置被配置为使得其电流可以比第一调节器相的能量存储装置中的电流更快地变化。

8. 发明申请

US20140117951A1 MULTI-STAGE POWER SUPPLY WITH FAST TRANSIENT RESPONSE 有权
标题翻译：具有快速瞬态响应的多级电源
公开(公告)号：US20140117951A1
公开(公告)日：2014-05-01
申请号：US13663903
申请日：2012-10-30
申请人： NVIDIA CORPORATION
发明人： William James Dally
IPC分类号： G05F1/10
CPC分类号： H02M3/158 , H02M3/1582 , H02M2001/007 , H02M2003/1566
摘要： Embodiments are disclosed relating to an electric power conversion device and methods for controlling the operation thereof. One disclosed embodiment provides a multi-stage electric power conversion device including a first regulator stage including a first stage energy storage device and a second regulator stage including a second stage energy storage device, the second stage energy storage device being operatively coupled between the first stage energy storage device and the load. The device further includes a control mechanism operative to control (i) a first stage output voltage on a node between the first stage energy storage device and the second stage energy storage device and (ii) a second stage output voltage on a node between the second stage energy storage device and the load.
摘要翻译：公开了关于电力转换装置的实施例以及用于控制其操作的方法。一个公开的实施例提供了一种多级电力转换装置，其包括第一调节器级，其包括第一级储能装置和包括第二级储能装置的第二调节器级，第二级储能装置可操作地耦合在第一级储能装置和负载。该装置还包括控制机构，其操作以控制（i）第一级能量存储装置与第二级能量存储装置之间的节点上的第一级输出电压和（ii）第二级能量存储装置之间的节点上的第二级输出电压阶段储能装置和负载。

9. 发明授权

US12118454B2 Neural network accelerator using logarithmic-based arithmetic 有权
公开(公告)号：US12118454B2
公开(公告)日：2024-10-15
申请号：US18537570
申请日：2023-12-12
申请人： NVIDIA Corporation
发明人： William James Dally , Rangharajan Venkatesan , Brucek Kurdo Khailany
IPC分类号： G06N3/063 , G06F7/483 , G06F17/16
CPC分类号： G06N3/063 , G06F7/4833 , G06F17/16
摘要： Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum. The sum may then be converted back into the logarithmic format.

10. 发明公开

US20240211166A1 HIERARCHICAL NETWORK FOR STACKED MEMORY SYSTEM 审中-公开
公开(公告)号：US20240211166A1
公开(公告)日：2024-06-27
申请号：US18438139
申请日：2024-02-09
申请人： NVIDIA Corporation
发明人： William James Dally , Carl Thomas Gray , Stephen W. Keckler , James Michael O'Connor
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.

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