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1. 发明授权

US10147222B2 Multi-pass rendering in a screen space pipeline 有权
公开(公告)号：US10147222B2
公开(公告)日：2018-12-04
申请号：US14952390
申请日：2015-11-25
申请人： NVIDIA CORPORATION
发明人： Ziyad Hakura , Cynthia Allison , Dale Kirkland , Jeffrey Bolz , Yury Uralsky , Jonah Alben
IPC分类号： G06T17/00 , G06T15/00 , G06T15/40 , G06T15/50 , G06T15/80 , G06T17/20 , G06T1/20
摘要： A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

2. 发明授权

US10032245B2 Techniques for maintaining atomicity and ordering for pixel shader operations 有权
公开(公告)号：US10032245B2
公开(公告)日：2018-07-24
申请号：US14924628
申请日：2015-10-27
申请人： NVIDIA CORPORATION
发明人： Ziyad Hakura , Eric Lum , Dale Kirkland , Jack Choquette , Patrick R. Brown , Yury Y. Uralsky , Jeffrey Bolz
IPC分类号： G06T1/20 , G06T1/60
摘要： A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

3. 发明申请

US20160077896A1 Techniques for Render Pass Dependencies in an API 有权
标题翻译： API中渲染通过依赖关系的技术
公开(公告)号：US20160077896A1
公开(公告)日：2016-03-17
申请号：US14856468
申请日：2015-09-16
申请人： NVIDIA Corporation
发明人： Jeffrey Bolz
IPC分类号： G06F9/54
CPC分类号： G06F9/54
摘要： Techniques for passing dependencies in an application programming interface API includes identifying a plurality of passes of execution commands. For each set of passes, wherein one pass is a destination pass and the other pass is a source pass to each other, one or more dependencies, of one or more dependency types, are determined between the execution commands of the destination pass and the source pass. Pass objects are then created for each identified pass, wherein each pass object records the execution commands and dependencies between the corresponding destination and source passes.
摘要翻译：用于在应用程序编程接口API中传递依赖性的技术包括识别执行命令的多个遍。对于每组通行证，其中一个通行证是目的地通行证，另一个通行证是彼此的源代码，一个或多个依赖类型的一个或多个依赖关系在目的地通行证的执行命令和源之间确定通过。然后为每个识别的通过创建传递对象，其中每个传递对象记录执行命令和对应的目标和源程序之间的依赖关系。

4. 发明授权

US10430989B2 Multi-pass rendering in a screen space pipeline 有权
公开(公告)号：US10430989B2
公开(公告)日：2019-10-01
申请号：US14952400
申请日：2015-11-25
申请人： NVIDIA CORPORATION
发明人： Ziyad Hakura , Cynthia Allison , Dale Kirkland , Jeffrey Bolz , Yury Uralsky , Jonah Alben
IPC分类号： G06T17/00 , G06T15/00 , G06T11/40
摘要： A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

5. 发明申请

US20180374185A1 Techniques for maintaining atomicity and ordering for pixel shader operations 审中-公开
公开(公告)号：US20180374185A1
公开(公告)日：2018-12-27
申请号：US15999185
申请日：2018-08-17
申请人： NVIDIA Corporation
发明人： Ziyad Hakura , Eric Lum , Dale Kirkland , Jack Choquette , Patrick R. Brown , Yury Y. Uralsky , Jeffrey Bolz
IPC分类号： G06T1/20 , G06T11/40 , G06T1/60
CPC分类号： G06T1/20 , G06T1/60 , G06T11/40
摘要： A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

6. 发明申请

US20150089151A1 SURFACE RESOURCE VIEW HASH FOR COHERENT CACHE OPERATIONS IN TEXTURE PROCESSING HARDWARE 有权
标题翻译：表面资源浏览用于纹理加工硬件中的高速缓存操作
公开(公告)号：US20150089151A1
公开(公告)日：2015-03-26
申请号：US14037212
申请日：2013-09-25
申请人： NVIDIA CORPORATION
发明人： Jeffrey Bolz , Patrick R. BROWN , Steven J. HEINRICH , Dale L. KIRKLAND , Joel MCCORMACK
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/1018 , G06F12/128 , G06F2212/455 , Y02D10/13
摘要： Techniques are disclosed for performing memory access operations. A texture unit receives a memory access operation that includes a tuple associated with a first view in a plurality of views. The texture unit retrieves a first hash value associated with a first texture header in a plurality of texture headers, where the first texture header is related to the first view. The texture unit retrieves a second hash value associated with a second texture header in the plurality of texture headers, where the second texture header is related to a second view. The texture unit determines whether the first view is potentially aliased with the second view, based on the first and second hash values. If so, then the texture unit invalidates a cache entry in a cache memory associated with the second texture header. Otherwise, the texture unit maintains the cache entry.
摘要翻译：公开了用于执行存储器访问操作的技术。纹理单元接收包括与多个视图中的第一视图相关联的元组的存储器访问操作。纹理单元检索与多个纹理标题中的第一纹理标题相关联的第一散列值，其中第一纹理标题与第一视图相关。纹理单元检索与多个纹理标题中的第二纹理标题相关联的第二散列值，其中第二纹理标题与第二视图相关。基于第一和第二哈希值，纹理单元确定第一视图是否与第二视图潜在地别名。如果是，则纹理单元使与第二纹理头相关联的高速缓冲存储器中的高速缓存条目无效。否则，纹理单元维护高速缓存条目。

7. 发明授权

US10019776B2 Techniques for maintaining atomicity and ordering for pixel shader operations 有权
公开(公告)号：US10019776B2
公开(公告)日：2018-07-10
申请号：US14924624
申请日：2015-10-27
申请人： NVIDIA CORPORATION
发明人： Ziyad Hakura , Eric Lum , Dale Kirkland , Jack Choquette , Patrick R. Brown , Yury Y. Uralsky , Jeffrey Bolz
IPC分类号： G06T1/20 , G06T1/60
CPC分类号： G06T1/20 , G06T1/60 , G06T11/40
摘要： A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

8. 发明申请

US20160321773A1 SYSTEM AND METHOD FOR CREATING ALIASED MAPPINGS TO MINIMIZE IMPACT OF CACHE INVALIDATION 审中-公开
标题翻译：创建映射映射的系统和方法，以最大限度地减少高速缓存的影响
公开(公告)号：US20160321773A1
公开(公告)日：2016-11-03
申请号：US14698024
申请日：2015-04-28
申请人： Nvidia Corporation
发明人： Jeffrey Bolz
IPC分类号： G06T1/20 , G06T1/60 , G09G5/395 , G06F12/08
CPC分类号： G06T1/20 , G06F9/3885 , G06F12/0808 , G06F12/0833 , G06F12/0888 , G06F2212/1024 , G06F2212/1041 , G06F2212/621 , G06T15/005 , G06T15/04 , G09G5/39 , G09G5/395 , G09G2340/10 , G09G2360/121
摘要： A parallel processor and a method of reducing texture cache invalidation are disclosed. In one embodiment, the parallel processor includes a cache configured to receive lines of data; and a parallel execution unit associated with the cache and configured to execute parallel counterparts of an operation. The parallel counterparts, when executed, are configured to create, in the cache, corresponding aliases of a line of data pertaining to the operation such that the parallel counterparts are operable to invalidate only the corresponding aliases.
摘要翻译：公开了并行处理器和减少纹理缓存失效的方法。在一个实施例中，并行处理器包括被配置为接收数据线的高速缓存器; 以及与所述高速缓存相关联并被配置为执行操作的并行对等物的并行执行单元。并行对等体在执行时被配置为在高速缓存中创建与该操作相关的一行数据的相应别名，使得并行对等体仅可操作以使仅对应的别名无效。

9. 发明申请

US20150242988A1 METHODS OF ELIMINATING REDUNDANT RENDERING OF FRAMES 审中-公开
标题翻译：消除框架冗余渲染的方法
公开(公告)号：US20150242988A1
公开(公告)日：2015-08-27
申请号：US14627496
申请日：2015-02-20
申请人： Nvidia Corporation
发明人： Jeffrey Bolz , Xinheng Li , Eric Lum , Emmett Kilgariff
IPC分类号： G06T1/20 , G06T3/40 , G06T11/60
CPC分类号： G06T1/20
摘要： A method for reducing redundant rendering of frames includes receiving draw calls including state information for a frame. The method includes generating respective bounding boxes for the draw calls. The bounding box is generated based on vertex data, vertex programs and transformation matrices. The method includes comparing the draw calls of the frame to the draw calls of one or more previous frames and identifying draw calls that are not identical in the compared frames. The method includes identifying the bounding boxes containing altered regions of the frames based on the draw calls that are not identical in the compared frames. The method includes reducing the altered regions into a smaller set of clip rectangles and rendering only inside the clip rectangles.
摘要翻译：用于减少帧的冗余渲染的方法包括接收包括帧的状态信息的绘制呼叫。该方法包括为绘制调用生成相应的边界框。边界框是基于顶点数据，顶点程序和变换矩阵生成的。该方法包括将帧的绘制调用与一个或多个先前帧的绘制调用进行比较，并且识别在比较帧中不相同的绘制调用。该方法包括基于在比较帧中不相同的绘制调用来识别包含帧的改变区域的边界框。该方法包括将改变的区域减少为较小的一组剪辑矩形并且仅在剪辑矩形内部呈现。

10. 发明授权

US10453168B2 Techniques for maintaining atomicity and ordering for pixel shader operations 有权
公开(公告)号：US10453168B2
公开(公告)日：2019-10-22
申请号：US15999185
申请日：2018-08-17
申请人： NVIDIA Corporation
发明人： Ziyad Hakura , Eric Lum , Dale Kirkland , Jack Choquette , Patrick R. Brown , Yury Y. Uralsky , Jeffrey Bolz
IPC分类号： G06T1/20 , G06T1/60 , G06T11/40
摘要： A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

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