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1. 发明授权

US5402374A Non-volatile semiconductor memory device and memory circuit using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器电路
公开(公告)号：US5402374A
公开(公告)日：1995-03-28
申请号：US235326
申请日：1994-04-29
申请人： Masataka Tsuruta , Noriyuki Shimoji , Hironobu Nakao , Takanori Ozawa
发明人： Masataka Tsuruta , Noriyuki Shimoji , Hironobu Nakao , Takanori Ozawa
IPC分类号： G11C17/00 , G11C16/04 , G11C16/16 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： H01L29/66825 , G11C16/16 , H01L21/2815 , H01L29/4232 , H01L29/7883
摘要： In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.
摘要翻译：在根据本发明的非易失性半导体存储器件中，浮置栅极通过隧道绝缘膜设置在介于源极区和漏极区之间的沟道区上。隧道绝缘膜和浮栅形成与源极区间隔开预定的偏移距离。与通道区域和浮动栅极绝缘的侧壁栅极设置在沟道区域上的偏移距离部分中。侧壁栅极正下方的偏移区域用作反转层，从而可以利用偏移区域的反转来高速读出信息。

2. 发明授权

US5332915A Semiconductor memory apparatus 失效
标题翻译：半导体存储装置
公开(公告)号：US5332915A
公开(公告)日：1994-07-26
申请号：US964043
申请日：1992-10-21
申请人： Noriyuki Shimoji , Takanori Ozawa , Hironobu Nakao
发明人： Noriyuki Shimoji , Takanori Ozawa , Hironobu Nakao
IPC分类号： G11C17/00 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/78 , H01L29/94
CPC分类号： H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/792
摘要： A high dielectric film instead of an oxidizing film conventionally used is used in the non-volatile memory of an MoNoS construction. Using a mixed film composed of a high dielectric constant film and an amorphous insulating film for the trap film, the ratio of the voltage applied to the tunnel oxidizing film is increased so that writing and erasing operations can be effected with a low voltage. Penetration of the electrons into the electrode and the flow of positive holes from the electrode are prevented so as to increase the flow efficiency.
摘要翻译：在MoNoS结构的非易失性存储器中使用代替常规使用的氧化膜的高介电膜。使用由高介电常数膜和非晶绝缘膜组成的混合膜用于陷阱膜，施加到隧道氧化膜的电压的比率增加，从而可以以低电压进行写入和擦除操作。防止电子进入电极的渗透和来自电极的空穴的流动，从而提高流动效率。

3. 发明授权

US5319229A Semiconductor nonvolatile memory with wide memory window and long data retention time 失效
标题翻译：具有宽内存窗口和长数据保留时间的半导体非易失性存储器
公开(公告)号：US5319229A
公开(公告)日：1994-06-07
申请号：US874497
申请日：1992-04-27
申请人： Noriyuki Shimoji , Takanori Ozawa , Hironobu Nakao
发明人： Noriyuki Shimoji , Takanori Ozawa , Hironobu Nakao
IPC分类号： H01L21/8247 , G11C16/04 , H01L21/28 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/34 , H01L29/68 , H01L29/78
CPC分类号： H01L21/28202 , G11C16/0466 , H01L29/513 , H01L29/518 , H01L29/792
摘要： A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.
摘要翻译：半导体非易失性存储器。存储单元具有以下结构。在P型硅衬底3中，设置有n +型源极26和n +型漏极28，两个区域形成沟道区30。在沟道区域30的顶部层叠有二氧化硅膜5，绝缘由氮化物膜18a，18b和18c以及氧化物膜20a，20b和20c组成的层。此外，在绝缘层的顶部，形成用作控制电极的多晶硅膜24。通过使用存储单元和行选择晶体管，可以构成半导体非易失性存储器。

4. 发明授权

US5331190A Semiconductor device including nonvolatile memories 失效
标题翻译：包括非易失性存储器的半导体器件
公开(公告)号：US5331190A
公开(公告)日：1994-07-19
申请号：US992915
申请日：1992-12-18
申请人： Noriyuki Shimoji , Hironobu Nakao
发明人： Noriyuki Shimoji , Hironobu Nakao
IPC分类号： G11C16/04 , G11C16/14 , H01L29/792 , H01L29/68 , G11C11/34 , H01L29/78
CPC分类号： H01L29/792 , G11C16/0416 , G11C16/14
摘要： The present invention provides nonvolatile semiconductor memory which has advantages permitting the cell of the memory circuit to integrate, the memory circuit to be easy to manufacture, and the manufacturing expense to be cut down. The nonvolatile memory (21) comprises a P type well for which a N+ type source (4) and a N+ type drain (3) is provided. A surface of a space between the source (4) and the drain (3) comprises a first portion (10a) and a second portion (10b). An insulating layer (6) for holding electrons spans the surface of the space. A memory gate electrode (5) is on the insulating layer (6) and spans the first portion (10a). The surface of the second portion (10b) and a part of the surface of the memory gate electrode (5) is covered with a first region electrode (24) attaching to the source (4). But the first region electrode (24) is insulated from the memory gate electrode (5) with the insulating layer (8).
摘要翻译：本发明提供了一种非易失性半导体存储器，其具有允许存储电路的单元集成，易于制造的存储器电路和要削减的制造费用的优点。非易失性存储器（21）包括提供N +型源极（4）和N +型漏极（3）的P型阱。源（4）和漏极（3）之间的空间的表面包括第一部分（10a）和第二部分（10b）。用于保持电子的绝缘层（6）跨越空间的表面。存储栅电极（5）位于绝缘层（6）上并跨越第一部分（10a）。第二部分（10b）的表面和存储栅电极（5）的表面的一部分被附接到源极（4）的第一区域电极（24）覆盖。但是第一区域电极（24）与具有绝缘层（8）的存储栅电极（5）绝缘。

5. 发明授权

US5286994A Semiconductor memory trap film assembly having plural laminated gate insulating films 失效
标题翻译：具有多个层叠栅绝缘膜的半导体存储器陷阱膜组件
公开(公告)号：US5286994A
公开(公告)日：1994-02-15
申请号：US902896
申请日：1992-06-23
申请人： Takanori Ozawa , Noriyuki Shimoji
发明人： Takanori Ozawa , Noriyuki Shimoji
IPC分类号： G11C17/00 , H01L21/28 , H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/68 , H01L29/34 , H01L29/78
CPC分类号： H01L29/513 , H01L29/518 , H01L29/792 , H01L21/28202
摘要： A trap film assembly of a semiconductor memory device includes a tunnel oxide layer formed on a semiconductor substrate and plural multi-layer film layers laminated on the tunnel oxide film. A thickness of each multi-layer film layer is sequentially increased in a direction away from the semiconductor substrate and towards a gate electrode, thereby displacing the charge centroid of the assembly towards the semiconductor substrate.
摘要翻译：半导体存储器件的陷阱膜组件包括形成在半导体衬底上的隧道氧化物层和层叠在隧道氧化物膜上的多个多层膜层。每个多层膜层的厚度在远离半导体衬底并朝向栅电极的方向上依次增加，从而将组件的电荷重心移向半导体衬底。

6. 发明授权

US5614766A Semiconductor device with stacked alternate-facing chips 失效
标题翻译：具有堆叠的交替面对芯片的半导体器件
公开(公告)号：US5614766A
公开(公告)日：1997-03-25
申请号：US556103
申请日：1995-11-09
申请人： Hidemi Takasu , Takanori Ozawa , Noriyuki Shimoji
发明人： Hidemi Takasu , Takanori Ozawa , Noriyuki Shimoji
IPC分类号： H01L25/065 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/85 , H01L25/0657 , H01L2224/05553 , H01L2224/16145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48472 , H01L2224/78301 , H01L2224/85181 , H01L2224/85205 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L24/45 , H01L24/78 , H01L2924/01013 , H01L2924/01033 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082
摘要： The present invention relates to a structure of semiconductor chip joint for mounting a plurality of semiconductor chips onto a single package. The joint comprises two or more semiconductor chips, the chips each having an element formation surface and a rear surface and being piled up with their element formation surfaces directed either in a first direction or in a second direction by turns so that their element formation surfaces are opposed to each other while their rear surfaces are opposed to each other, a bonding pad provided on the element formation surface of the chip directed in the first direction, connecting pad provided on the element formation surface of the chip directed both in the first direction and in the second direction;wherein the chip whose element formation surface is directed in the second direction is piled on so that the bonding pad of the chip whose element formation surface is directed in the first direction is exposed, and the chip whose element formation surface is directed in the first direction and the chip whose element formation surface is directed in the second direction are electrically connected to each other through their respective connecting pads with a conductive bump.
摘要翻译：本发明涉及用于将多个半导体芯片安装到单个封装上的半导体芯片接头的结构。接头包括两个或更多个半导体芯片，每个芯片均具有元件形成表面和后表面，并且它们的元件形成表面被堆积在其第一方向或第二方向上，以使它们的元件形成表面是在其后表面彼此相对的情况下彼此相对;焊盘，设置在沿着第一方向指向的芯片的元件形成表面上;连接焊盘，设置在芯片的元件形成表面上，两者沿第一方向指向;以及在第二个方向其中将元件形成表面朝向第二方向的芯片堆叠在一起，使得元件形成表面沿第一方向指向的芯片的焊盘露出，并且其元件形成表面沿第一方向并且其元件形成表面在第二方向上引导的芯片通过其各自的连接焊盘彼此电连接，并具有导电凸块。

7. 发明授权

US07928649B2 Organic luminescent device 有权
标题翻译：有机发光装置
公开(公告)号：US07928649B2
公开(公告)日：2011-04-19
申请号：US12317262
申请日：2008-12-19
申请人： Noriyuki Shimoji
发明人： Noriyuki Shimoji
IPC分类号： H01J1/62
CPC分类号： H05B33/10 , H01L51/5212 , H01L51/5268 , H01L51/5271 , H05B33/26 , H05B33/28
摘要： An organic luminescent device according to the present invention includes a substrate, an organic luminescent layer, and a reflection electrode. Here, the substrate has first and second principal surfaces opposed to each other; the organic luminescent layer is arranged on the first principal surface of the substrate, and is held between a pair of electrodes at least one of which is a transparent electrode; and the reflection electrode is adjacent to a luminescent area of the organic luminescent layer and is arranged on a front surface or a back surface of the transparent electrode. The transparent electrode is arranged on the first principal surface of the substrate, while the reflection electrode is arranged on the transparent electrode. The second principal surface of the substrate is formed into a rough surface at least on its part opposed to the reflection electrode. This configuration improves light extraction efficiency.
摘要翻译：根据本发明的有机发光装置包括基板，有机发光层和反射电极。这里，基板具有彼此相对的第一和第二主表面; 有机发光层配置在基板的第一主面上，并且被保持在一对电极中，其中至少一个是透明电极; 反射电极与有机发光层的发光区域相邻，配置在透明电极的正面或背面。透明电极布置在基板的第一主表面上，而反射电极布置在透明电极上。基板的第二主表面至少在其与反射电极相对的部分上形成为粗糙表面。该结构提高光提取效率。

8. 发明授权

US07354864B2 Method of producing semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07354864B2
公开(公告)日：2008-04-08
申请号：US11276320
申请日：2006-02-24
申请人： Noriyuki Shimoji , Masaki Takaoka
发明人： Noriyuki Shimoji , Masaki Takaoka
IPC分类号： H01L21/302
CPC分类号： F04B43/043 , B81B2203/0353 , B81C1/00626 , B81C2201/0136 , H01L29/0657
摘要： A method of producing a semiconductor device is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.
摘要翻译：公开了一种制造半导体器件的方法，其中在半导体衬底的上表面中形成有从其下表面的通孔，并且所需尺寸的开口形成在所述半导体衬底的上表面上的期望位置基质。在半导体衬底中形成用作蚀刻阻挡层的引导件。在导向件中形成宽度为W 2的开口。开口面向形成通孔所使用的掩模中的开口，其宽度W 2比掩模中的开口的宽度W 4窄。蚀刻进行的方向由蚀刻形成在导向器中的开口控制，从基板的下表面传导到基板的上表面，因此宽度W 1和上部开口的位置的偏差可以控制基板的表面。

9. 发明授权

US5760437A Semiconductor memory device, a method for manufacturing thereof and a connecting method of virtual ground array of a semiconductor memory device 失效
标题翻译：半导体存储器件和半导体存储器的虚拟接地阵列的连接
公开(公告)号：US5760437A
公开(公告)日：1998-06-02
申请号：US711533
申请日：1996-09-10
申请人： Noriyuki Shimoji
发明人： Noriyuki Shimoji
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0491 , H01L27/115 , H01L27/11519 , H01L27/11521
摘要： An independent active region K42 is composed by consecutively providing the source region S42 and S53 of the memory cell MC42 and MC53 between the word line WL2, WL3. The memory cell MC42 and MC53 are connected to the word line WL2, WL3 respectively. Another independent active region K53 is composed by consecutively providing the drain region D53 and D64 of the memory cell MC53 and MC64 between the word line WL3, WL4. The bit line BL3 is formed by connecting each of the independent active regions K30, K31, K32 and K33 with polysilicon respectively. Each of the independent active regions include each of the drain regions D41, D42, D43 and D44 of the memory cells MC41, MC42, MC43 and MC44. Also, the bit line BL4 is formed by connecting each of the independent active regions K41, K42, K43 and K44 with polysilicon respectively. Each of the independent active regions comprises the source regions S41, S42, S43 and S44 respectively.
摘要翻译：独立的有源区域K42由在字线WL2，WL3之间连续地提供存储单元MC42的源极区域S42和S53以及MC53构成。存储单元MC42和MC53分别连接到字线WL2，WL3。另一个独立的有源区K53由在字线WL3，WL4之间连续提供存储单元MC53和MC64的漏区D53和D64组成。通过将独立的有源区域K30，K31，K32和K33分别与多晶硅分别连接来形成位线BL3。每个独立的有源区包括存储单元MC41，MC42，MC43和MC44的漏极区D41，D42，D43和D44中的每一个。此外，位线BL4通过分别将多个独立的有源区域K41，K42，K43和K44分别连接到多晶硅中而形成。每个独立的有源区域分别包括源极区域S41，S42，S43和S44。

10. 发明授权

US5420458A Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5420458A
公开(公告)日：1995-05-30
申请号：US310011
申请日：1994-09-21
申请人： Noriyuki Shimoji
发明人： Noriyuki Shimoji
IPC分类号： H01L21/762 , H01L21/316 , H01L21/76 , H01L27/12 , H01L29/68 , H01L27/04 , H01L29/06
CPC分类号： H01L21/76264 , H01L21/76297 , H01L27/12 , H01L21/76281 , H01L21/76289 , H01L2924/10158
摘要： A semiconductor device having a high-speed device and a uniform plane bearing is provided. Device formation regions (51, 52, and 55) are formed on upper surfaces of the silicon substrate (21 and 22), and device isolation regions (9) acting as insulating layer are formed therebetween. The silicon substrate is etched to shape a bottom recessed part (8). The bottom recessed part (8) is formed in such a manner that it borders on the device isolation region (9) and allows the device formation regions (51, 52, and 55) to be emerged therefrom. This structure enables a pn junction to be eliminated, realizing a semiconductor device capable of high-speed operation. Further, each device is formed in an N.sup.- type silicon layer (22) which is grown from the silicon substrate, and thereafter is insulated by forming the bottom recessed part (8). Accordingly, the semiconductor device has a uniform plane bearing.
摘要翻译：提供了具有高速装置和均匀平面轴承的半导体装置。器件形成区域（51,52和55）形成在硅衬底（21和22）的上表面上，并且在它们之间形成用作绝缘层的器件隔离区域（9）。蚀刻硅衬底以形成底部凹陷部分（8）。底部凹陷部分（8）以与装置隔离区（9）相接合的方式形成，并允许装置形成区（51,52和55）从其中排出。该结构能够消除pn结，实现能够高速运转的半导体器件。此外，每个器件形成在从硅衬底生长的N-型硅层（22）中，然后通过形成底部凹陷部分（8）而被绝缘。因此，半导体器件具有均匀的平面轴承。

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