专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07760625B2 Exchange node and exchange node control method 失效
标题翻译：交换节点和交换节点控制方法
公开(公告)号：US07760625B2
公开(公告)日：2010-07-20
申请号：US11577215
申请日：2005-09-16
申请人： Noriharu Miyaho , Kazunori Miyahara
发明人： Noriharu Miyaho , Kazunori Miyahara
IPC分类号： H04L12/26 , H04L12/28 , H04J3/00
CPC分类号： H04L47/10 , H04L12/5601 , H04L43/0882 , H04L47/12 , H04L47/2408 , H04L47/283 , H04L49/602
摘要： The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced.The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10. More preferably, a frame compression circuit 16, a frame decompression circuit 18 and a priority determination circuit 20 are arranged.
摘要翻译：本发明通过监视交换节点的输出/分配单元来将延迟时间缩短到非常短，以将未使用的时隙指定为数据的写入目的地，并通过数据中包含的优先级控制信号执行优先级控制。通过执行到指定时隙的写入输出来解决交通拥堵，而不管数据的传输路径的通信速度如何。此外，本发明的目的是提供一种交换节点和交换节点控制方法，其通过使用连接类型作为通信方法来确保通信质量，因为可以减少通信中的延迟时间。根据本发明的交换节点100包括输入缓冲单元2，识别单元7，分发单元5，复用电路9，时隙分配电路12和输出/分配单元10.更优选地，帧压缩电路16，帧解压缩电路18和优先级确定电路20。

2. 发明申请

US20080084898A1 EXCHANGE NODE AND EXCHANGE NODE CONTROL METHOD 失效
标题翻译：交换节点和交换节点控制方法
公开(公告)号：US20080084898A1
公开(公告)日：2008-04-10
申请号：US11577215
申请日：2005-09-16
申请人： Noriharu Miyaho , Kazunori Miyahara
发明人： Noriharu Miyaho , Kazunori Miyahara
IPC分类号： H04J3/00
CPC分类号： H04L47/10 , H04L12/5601 , H04L43/0882 , H04L47/12 , H04L47/2408 , H04L47/283 , H04L49/602
摘要： The present invention reduces the delay time to extremely short by monitoring the output/distribution unit of the exchange node to specify the unused time slot as write destination of the data and performing priority control by the priority control signal contained in the data. The traffic congestion is resolved by performing write output to the specified time slot regardless of the communication speed of the transmission path of the data. Furthermore, the present invention aims to provide the exchange node and the exchange node control method that ensures communication quality by using the connection type as the communication method since the delay time in communication can be reduced.The exchange node 100 according to the present invention includes an input buffer unit 2, an identification unit 7, a distribution unit 5, a multiplexing circuit 9, a time slot allocation circuit 12, and an output/distribution unit 10. More preferably, a frame compression circuit 16, a frame decompression circuit 18 and a priority determination circuit 20 are arranged.
摘要翻译：本发明通过监视交换节点的输出/分配单元来将延迟时间缩短到非常短，以将未使用的时隙指定为数据的写入目的地，并通过数据中包含的优先级控制信号执行优先级控制。通过执行到指定时隙的写入输出来解决交通拥堵，而不管数据的传输路径的通信速度如何。此外，本发明的目的是提供一种交换节点和交换节点控制方法，其通过使用连接类型作为通信方法来确保通信质量，因为可以减少通信中的延迟时间。根据本发明的交换节点100包括输入缓冲单元2，识别单元7，分发单元5，多路复用电路9，时隙分配电路12和输出/分配单元10。更优选地，布置了帧压缩电路16，帧解压缩电路18和优先级确定电路20。

3. 发明授权

US4575844A Digital switching system 失效
标题翻译：数字交换系统
公开(公告)号：US4575844A
公开(公告)日：1986-03-11
申请号：US615438
申请日：1984-05-30
申请人： Yasuharu Kosuge , Noriharu Miyaho
发明人： Yasuharu Kosuge , Noriharu Miyaho
IPC分类号： H04Q11/04 , H04L12/64
CPC分类号： H04L12/64
摘要： A hierarchical message channel storage of a digital switching system which is connected to time division multiplex transmission lines includes at least a small-capacity high-speed memory and a large-capacity low-speed memory. A control section performs switching using the high-speed memory when a circuit switching call is received. However, when a packet switching call is received, the control section accesses the high-speed memory to temporarily store transmission data in the high-speed memory and performs switching for one of the output transmission lines or the control section accesses the high- and low-speed memories to temporarily store data in the low-speed memory through said high-speed memory so as to perform switching for one of said output transmission lines. In this case, the access cycles of the high-speed memory have circuit/packet switching call cycles and switching program cycles. A single storage is commonly used for the circuit switching call requiring writing data at a high speed, the packet switching call requiring storing a great amount of data, and the switching program.
摘要翻译：连接到时分复用传输线的数字交换系统的分层消息信道存储器至少包括小容量高速存储器和大容量低速存储器。当接收到电路切换呼叫时，控制部分使用高速存储器执行切换。然而，当接收到分组交换呼叫时，控制部分访问高速存储器以将传输数据临时存储在高速存储器中，并且对输出传输线之一执行切换，或者控制部分访问高低速速度存储器，用于通过所述高速存储器临时存储低速存储器中的数据，以便对所述输出传输线之一执行切换。在这种情况下，高速存储器的访问周期具有电路/分组交换呼叫周期和切换程序周期。单个存储器通常用于需要高速写入数据的电路交换呼叫，需要存储大量数据的分组交换呼叫以及切换程序。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式