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1. 发明授权

US07930514B2 Method, system, and computer program product for implementing a dual-addressable cache 失效
标题翻译：用于实现双重寻址缓存的方法，系统和计算机程序产品
公开(公告)号：US07930514B2
公开(公告)日：2011-04-19
申请号：US11054298
申请日：2005-02-09
申请人： Norbert Hagspiel , Erwin Pfeffer , Bruce A. Wagar
发明人： Norbert Hagspiel , Erwin Pfeffer , Bruce A. Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.
摘要翻译：提供了一种用于实现双重寻址缓存的方法，系统和计算机程序产品。该方法包括为缓存目录中提供的每个同余类添加间接索引的字段。缓存目录由主地址索引。响应于基于对应于主地址的已知辅助地址的主地址的请求，该方法还包括生成辅助地址的索引，以及将间接索引中的一个插入或更新到一个字段中以用于一致与次要地址相关的课程。为间接索引分配与主地址相对应的虚拟索引的值。该方法还包括搜索辅助地址的每个间接索引的同余类。

2. 发明申请

US20080320216A1 Translation Lookaside Buffer and Related Method and Program Product Utilized For Virtual Addresses 失效
标题翻译：用于虚拟地址的翻译后备缓冲区和相关方法和程序产品
公开(公告)号：US20080320216A1
公开(公告)日：2008-12-25
申请号：US12142885
申请日：2008-06-20
申请人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
发明人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
IPC分类号： G06F12/00
CPC分类号： G06F12/1036
摘要： A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM.
摘要翻译：提供了一种程序产品，翻译后备缓冲器和用于操作TLB的相关方法。该方法包括以下步骤：a）当向所述TLB添加虚拟地址的条目时，测试所述虚拟地址的属性数据是否已经存储在所述CAM中，并且属性数据是否已经存储在所述CAM中，生成标签用于所述虚拟地址的数据，使得所述标签数据不同于当前存储在所述RAM中并与所述CAM中的新条目相关联的用于属性数据的其他虚拟地址生成的标签数据，将生成的标签数据添加到所述RAM，到所述CAM中的相关联的条目，并且在所述CAM中为所述相关联的条目设置有效标志; 否则如果属性数据已经存储在所述CAM中，则将存储的属性数据添加到用于所述虚拟地址的所述RAM中的条目; 并且当执行TLB查找操作时：从与所述RAM中的所述虚拟地址的条目相关联的所述CAM中的条目读取有效性标志和标签数据，并同时从所述条目读取绝对地址和标签数据在所述RAM中用于所述虚拟地址，并且仅当从所述CAM读取的标签数据有效并且与从所述RAM读取的标签数据匹配时才产生TLB命中。

3. 发明授权

US08166239B2 Translation lookaside buffer and related method and program product utilized for virtual addresses 失效
标题翻译：翻译后备缓冲区以及用于虚拟地址的相关方法和程序产品
公开(公告)号：US08166239B2
公开(公告)日：2012-04-24
申请号：US12142885
申请日：2008-06-20
申请人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
发明人： Matthias Fertig , Ute Gaertner , Norbert Hagspiel , Erwin Pfeffer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1036
摘要： A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM.
摘要翻译：提供了一种程序产品，翻译后备缓冲器和用于操作TLB的相关方法。该方法包括以下步骤：a）当向所述TLB添加虚拟地址的条目时，测试所述虚拟地址的属性数据是否已经存储在所述CAM中，并且属性数据是否已经存储在所述CAM中，生成标签用于所述虚拟地址的数据，使得所述标签数据不同于当前存储在所述RAM中并与所述CAM中的新条目相关联的用于属性数据的其他虚拟地址生成的标签数据，将生成的标签数据添加到所述RAM，到所述CAM中的相关联的条目，并且在所述CAM中为所述相关联的条目设置有效标志; 否则如果属性数据已经存储在所述CAM中，则将存储的属性数据添加到用于所述虚拟地址的所述RAM中的条目; 并且当执行TLB查找操作时：从与所述RAM中的所述虚拟地址的条目相关联的所述CAM中的条目读取有效性标志和标签数据，并同时从所述条目读取绝对地址和标签数据在所述RAM中用于所述虚拟地址，并且仅当从所述CAM读取的标签数据有效并且与从所述RAM读取的标签数据匹配时才产生TLB命中。

4. 发明授权

US06766434B2 Method for sharing a translation lookaside buffer between CPUs 有权
标题翻译：在CPU之间共享翻译后备缓冲区的方法
公开(公告)号：US06766434B2
公开(公告)日：2004-07-20
申请号：US10126239
申请日：2002-04-19
申请人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
发明人： Ute Gaertner , Norbert Hagspiel , Frank Lehnert , Erwin Pfeffer , Kerstin Schelm
IPC分类号： G06F1208
CPC分类号： G06F12/1027
摘要： The present invention generally relates to shared-memory multiprocessor systems, such as IBM ESA/390 or RS/6000 systems, and deals more particularly with a method and system for sharing a second-level translation lookaside buffer (TLB 2) between several CPUs (30a, . . . 30d) for improving the performance and reducing the chip area required to buffer the results of virtual-to-absolute address translations. The inventive TLB2 organization comprises several small arrays (32a, . . . 32d) dedicated to particular CPUs, providing an interface to a major array (21), which is shared between the CPUs. The dedicated arrays 32a, . . . 32d) are required to fulfill the architected constraints and link several CPUs to the commonly used shared array (21).
摘要翻译：本发明一般涉及诸如IBM ESA / 390或RS / 6000系统的共享存储器多处理器系统，更具体地涉及用于在多个CPU之间共享第二级转换后备缓冲器（TLB 2）的方法和系统（ 30a，... 30d），用于提高性能并减少缓冲虚拟到绝对地址转换结果所需的芯片面积。本发明的TLB2组织包括专用于特定CPU的几个小阵列（32a，...，32d），提供与CPU之间共享的主阵列（21）的接口。专用阵列32a，。。。 32d）需要满足架构约束并将多个CPU链接到常用的共享阵列（21）。

5. 发明申请

US20060179233A1 Method, system, and computer program product for implementing a dual-addressable cache 失效
标题翻译：用于实现双重寻址缓存的方法，系统和计算机程序产品
公开(公告)号：US20060179233A1
公开(公告)日：2006-08-10
申请号：US11054298
申请日：2005-02-09
申请人： Norbert Hagspiel , Erwin Pfeffer , Bruce Wagar
发明人： Norbert Hagspiel , Erwin Pfeffer , Bruce Wagar
IPC分类号： G06F12/00
CPC分类号： G06F12/0864
摘要： A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. In response to a request for a primary address based upon a known secondary address corresponding to the primary address, the method also includes generating an index for the secondary address, and inserting or updating one of the indirect indices into one of the fields for a congruence class relating to the secondary address. The indirect index is assigned a value of a virtual index corresponding to the primary address. The method further includes searching congruence classes of each of the indirect indices for the secondary address.
摘要翻译：提供了一种用于实现双重寻址缓存的方法，系统和计算机程序产品。该方法包括为缓存目录中提供的每个同余类添加间接索引的字段。缓存目录由主地址索引。响应于基于对应于主地址的已知辅助地址的主地址的请求，该方法还包括生成辅助地址的索引，以及将间接索引中的一个插入或更新到一个字段中以用于一致与次要地址相关的课程。为间接索引分配与主地址相对应的虚拟索引的值。该方法还包括搜索辅助地址的每个间接索引的同余类。

6. 发明申请

US20120011341A1 Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field 有权
标题翻译：基于地址转换格式控制字段加载页表输入地址指令执行
公开(公告)号：US20120011341A1
公开(公告)日：2012-01-12
申请号：US13234374
申请日：2011-09-16
申请人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Gustav E. Sittmann
发明人： Dan F. Greiner , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Gustav E. Sittmann
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/651 , G06F2212/652
摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.
摘要翻译：提供了为计算机系统的机器结构定义的加载页表项地址函数。在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。基于M场的内容，获得具有至少一个分段表的地址转换表的层次结构的初始起始地址。基于获得的初始起始地址，执行动态地址转换，直到获得页表项。页表入口地址保存在识别的第一个通用寄存器中。

7. 发明授权

US08082405B2 Dynamic address translation with fetch protection 有权
标题翻译：动态地址转换带保护
公开(公告)号：US08082405B2
公开(公告)日：2011-12-20
申请号：US11972682
申请日：2008-01-11
申请人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
发明人： Dan F. Greiner , Charles W. Gainey, Jr. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1475 , G06F12/1036 , G06F12/109
摘要： In an enhanced dynamic address translation facility a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are used to access a segment table entry containing a format control field and an access validity field. If the format control field is enabled, the segment table entry further contains an access control field and a fetch protection field and a segment-frame absolute address. Fetch operations from the desired block of data are permitted if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译：在增强型动态地址转换装置中，使用要转换的虚拟地址和转换表层级的转换表的初始起始地址来访问包含格式控制字段和访问有效性字段的段表条目。如果格式控制字段被使能，则段表条目还包含访问控制字段和取指保护字段和段帧绝对地址。如果与虚拟地址相关联的程序访问密钥等于段访问控制字段，则允许从所需数据块获取操作。

8. 发明授权

US07975182B2 Method, system and computer program product for generating trace data 失效
标题翻译：用于生成跟踪数据的方法，系统和计算机程序产品
公开(公告)号：US07975182B2
公开(公告)日：2011-07-05
申请号：US12036430
申请日：2008-02-25
申请人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
发明人： Debbie A. St. Onge , Jane H. Bartik , Barry W. Krumm , Erwin Pfeffer , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3461 , G06F2201/885
摘要： There is provided a method, system and computer program product for generating trace data related to a data processing system event. The method includes: receiving an instruction relating to the system event from a location in the system; determining a minimum number of trace segment records required to record instruction information; and creating a trace segment table including the number of trace segment records, the number of trace segment records including at least one instruction record.
摘要翻译：提供了一种用于生成与数据处理系统事件相关的跟踪数据的方法，系统和计算机程序产品。该方法包括：从系统中的位置接收与系统事件有关的指令; 确定记录指令信息所需的跟踪段记录的最小数量; 并创建包括跟踪段记录的数量的跟踪段表，包括至少一个指令记录的跟踪段记录的数目。

9. 发明申请

US20090216992A1 DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER 有权
标题翻译：动态地址翻译与翻译例外的合格者
公开(公告)号：US20090216992A1
公开(公告)日：2009-08-27
申请号：US12037268
申请日：2008-02-26
申请人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer
发明人： DAN F. GREINER , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer
IPC分类号： G06F12/10
CPC分类号： G06F12/0284 , G06F3/0604 , G06F3/0667 , G06F3/067 , G06F9/455 , G06F12/10 , G06F12/1009 , G06F12/1036 , G06F12/109 , G06F2212/1032 , G06F2212/152 , G06F2212/50 , G06F2212/652 , G06F2212/657
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。虚拟地址的动态地址转换进行。响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

10. 发明申请

US20090182974A1 DYNAMIC ADDRESS TRANSLATION WITH ACCESS CONTROL 有权
标题翻译：动态地址翻译与访问控制
公开(公告)号：US20090182974A1
公开(公告)日：2009-07-16
申请号：US11972682
申请日：2008-01-11
申请人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
发明人： DAN F. GREINER , Charles W. Gainey, JR. , Lisa C. Heller , Damian L. Osisek , Erwin Pfeffer , Timothy J. Slegel , Charles E. Webb
IPC分类号： G06F12/10
CPC分类号： G06F12/1475 , G06F12/1036 , G06F12/109
摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.
摘要翻译：提供的是增强的动态地址转换设施。在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。基于原始地址，获得包含格式控制字段和访问有效性字段的段表条目。如果启用格式控制和访问有效性，则段表条目还包含访问控制和提取保护字段以及段帧绝对地址。仅当访问控制字段与由程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许对数据块进行存储操作。只有当与虚拟地址相关联的程序访问密钥等于段访问控制字段时，才允许从所需数据块获取操作。

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