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1. 发明授权

US06739388B2 Air-conditioning system for a vehicle 有权
标题翻译：汽车空调系统
公开(公告)号：US06739388B2
公开(公告)日：2004-05-25
申请号：US10198460
申请日：2002-07-19
申请人： Nobuya Nakagawa , Toshihisa Kondo , Kazuo Ishii , Masashi Fujita
发明人： Nobuya Nakagawa , Toshihisa Kondo , Kazuo Ishii , Masashi Fujita
IPC分类号： B60H100
CPC分类号： B60H1/00207 , B60H1/00007 , B60H1/00028 , B60H2001/00107
摘要： An air conditioning system mountable in the rear of a vehicle having a vent mode and a foot mode is disclosed. The air conditioning system comprises a casing, an evaporator mounted at an upper front portion within the casing, a heater core mounted below the evaporator such that the evaporator and the heater core are not superposed when seen in a vehicle front-to-rear direction. A temperature controlling damper is provided for controlling rate of air which is directed toward the heater core so as to attain a selected final temperature of the air which is discharged into a passenger compartment of the vehicle. Vent and foot outlets are also provided.
摘要翻译：公开了一种安装在具有通气模式和脚踏模式的车辆后部的空调系统。空调系统包括壳体，安装在壳体内的上前部的蒸发器，安装在蒸发器下方的加热器芯，使得当在车辆前后方向上观察时，蒸发器和加热器芯不重叠。设置有温度控制阻尼器，用于控制朝向加热器芯的空气的速率，以获得排出到车辆的乘客室中的空气的选定的最终温度。还提供排气口和脚座。

2. 发明授权

US08787083B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US08787083B2
公开(公告)日：2014-07-22
申请号：US13365999
申请日：2012-02-03
申请人： Masashi Fujita
发明人： Masashi Fujita
IPC分类号： G11C11/34 , G11C14/00 , G11C7/00 , G11C5/00 , G11C5/06 , H01L29/788 , H01L29/792
CPC分类号： G11C11/40 , G11C5/005 , G11C5/06 , G11C7/00 , G11C7/20 , G11C11/34 , G11C14/00 , G11C14/0009 , G11C14/0054 , H01L29/7869 , H01L29/788 , H01L29/792
摘要： While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit.
摘要翻译：在电源供应停止的情况下，可以将保持在易失性存储部中的数据信号保持在非易失性存储部。在非易失性存储器部分中，具有极低截止电流的晶体管允许数据信号长时间保持在电容器中。因此，即使在停止供电时，非易失性存储部也能够保持逻辑状态。当再次开始供电时，在电源供应停止时保持在电容器中的数据信号被设定为通过接通复位电路而不发生故障的电位。

3. 发明授权

US08681533B2 Memory circuit, signal processing circuit, and electronic device 有权
标题翻译：存储电路，信号处理电路和电子设备
公开(公告)号：US08681533B2
公开(公告)日：2014-03-25
申请号：US13453135
申请日：2012-04-23
申请人： Masashi Fujita
发明人： Masashi Fujita
IPC分类号： G11C11/24
CPC分类号： H01L27/00 , G11C7/1006 , G11C11/401 , G11C14/0009 , H01L27/1225
摘要： A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided.
摘要翻译：提供了使用具有新颖结构的非易失性存储器电路的信号处理电路。非易失性存储器电路使用包括氧化物半导体的晶体管和连接到晶体管的源极和漏极之一的电容器来形成。高电位电位被预先写入存储电路，并且在保存数据具有高电位电位的情况下保持该状态，而在存储电路中写入低电位电位的情况下，要保存的数据具有低级潜力。因此，可以提供具有改善的写入速度的信号处理电路。

4. 发明授权

US08328105B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08328105B2
公开(公告)日：2012-12-11
申请号：US12732863
申请日：2010-03-26
申请人： Masashi Fujita
发明人： Masashi Fujita
IPC分类号： G06K19/06
CPC分类号： G06K19/0723 , G06K19/0701 , G06K19/0715
摘要： An object is to provide a semiconductor device which operates stably even when the communication distance between a reader/writer and a non-contact data carrier is largely changed. A protection circuit is provided in the non-contact data carrier, and an operating state and a non-operating state of the protection circuit are switched depending on the communication distance between the reader/writer and the non-contact data carrier. The operating point at which the operating state and the non-operating state of the protection circuit are switched is different between the case where input voltage of the protection circuit is low in an initial state and then gradually raised and the case where input voltage of the protection circuit is high in an initial state and then gradually lowered.
摘要翻译：目的在于提供即使当读写器与非接触式数据载体之间的通信距离发生很大变化时也能够稳定地工作的半导体装置。在非接触数据载体中提供保护电路，并且根据读/写器和非接触数据载体之间的通信距离来切换保护电路的操作状态和非操作状态。保护电路的工作状态和非工作状态切换的工作点在初始状态下保护电路的输入电压为低，然后逐渐升高的情况与输入电压保护电路处于初始状态，然后逐渐降低。

5. 发明申请

US20120287703A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120287703A1
公开(公告)日：2012-11-15
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/24
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

6. 发明授权

US08174229B2 Sample stage apparatus and method of controlling the same 有权
标题翻译：样品台装置及其控制方法
公开(公告)号：US08174229B2
公开(公告)日：2012-05-08
申请号：US12420358
申请日：2009-04-08
申请人： Masashi Fujita , Shuichi Nakagawa , Takashi Kobayashi
发明人： Masashi Fujita , Shuichi Nakagawa , Takashi Kobayashi
IPC分类号： B64C17/06
CPC分类号： H01J37/20 , H01J2237/20228 , H01J2237/20285 , H01J2237/20292
摘要： The present invention provides a stage apparatus capable of reducing a positioning time without increasing a positional deviation. A positioning control method of a sample stage apparatus includes: a high-speed movement step of moving a table to a high-speed movement target position at a first movement speed; a positional deviation correcting step of moving the table to a low-speed positioning step start position at a second movement speed that is lower than the first movement speed; a low-speed positioning step of moving the table to a target position at a third movement speed that is lower than the second movement speed. After the low-speed positioning step is completed, a rod connected to a motor returns to its original position to separate a pin of the rod side from a concave portion of the table side.
摘要翻译：本发明提供一种能够在不增加位置偏差的情况下减少定位时间的舞台装置。采样台装置的定位控制方法包括：以第一移动速度将桌子移动到高速移动目标位置的高速移动步骤; 位置偏差校正步骤，以低于第一移动速度的第二移动速度将桌子移动到低速定位步骤开始位置; 低速定位步骤，以低于第二移动速度的第三移动速度将桌子移动到目标位置。在低速定位步骤完成之后，连接到电动机的杆返回到其原始位置，以将杆侧的销与台侧的凹部分开。

7. 发明授权

US08036604B2 Transmitting and receiving circuit and semiconductor device including the same 有权
标题翻译：发射和接收电路和包括其的半导体器件
公开(公告)号：US08036604B2
公开(公告)日：2011-10-11
申请号：US12003112
申请日：2007-12-20
申请人： Masashi Fujita , Yutaka Shionoiri
发明人： Masashi Fujita , Yutaka Shionoiri
IPC分类号： H04B1/38
CPC分类号： H03F1/56 , H03F1/0205 , H03F3/245 , H03F2200/327
摘要： An object is to provide a circuit configuration with which the number of transistors can be reduced and power conversion efficiency can be prevented from being reduced, in a transmitting and receiving circuit. The transmitting and receiving circuit includes a voltage doubler rectifier circuit having N stages, each of which includes a capacitor, where N is a positive integer. The voltage doubler rectifier circuit having N stages is connected to a circuit having a modulation function. In the capacitor in any one of the N stages, one electrode of the one capacitor is connected to an input terminal of the transmitting and receiving circuit, and a node to which the other electrode of the one capacitor is connected is connected to a circuit having a demodulation function. Since the transmitting and receiving circuit can be formed of fewer transistors, it can be reduced in size. Since a reduction in power conversion efficiency can be prevented, a power supply potential can be efficiently generated.
摘要翻译：目的在于提供一种在发送和接收电路中可以减少晶体管数量并且可以防止功率转换效率降低的电路配置。发送和接收电路包括具有N级的倍压整流电路，每个级包括电容器，其中N是正整数。具有N级的倍压整流电路连接到具有调制功能的电路。在N级中的任何一级的电容器中，一个电容器的一个电极连接到发送和接收电路的输入端子，并且连接一个电容器的另一个电极的节点连接到具有解调功能。由于发送和接收电路可以由更少的晶体管形成，所以可以减小其尺寸。由于可以防止功率转换效率的降低，所以可以有效地产生电源电位。

8. 发明授权

US07901521B2 Aluminum base alloy 失效
标题翻译：铝基合金
公开(公告)号：US07901521B2
公开(公告)日：2011-03-08
申请号：US12057985
申请日：2008-03-28
申请人： Masashi Fujita , Akihisa Inoue , Hisamichi Kimura
发明人： Masashi Fujita , Akihisa Inoue , Hisamichi Kimura
IPC分类号： C22C45/08
CPC分类号： C22C45/08
摘要： An aluminum base alloy is produced by supercooling a molten alloy composed mainly of aluminum. The molten alloy contains an element capable of forming a quasicrystalline phase, an element which aids formation of the quasicrystals, and an element which stabilizes a supercooled state of the molten alloy and delays crystallization of a crystalline phase, and is composed of a mixed composition of a fine amorphous phase and an aluminum crystalline phase or an aluminum supersaturated solid solution phase, or a single phase of only an amorphous phase.
摘要翻译：铝基合金是通过过冷化由铝构成的熔融合金制成的。熔融合金含有能够形成准晶相的元素，有助于形成准晶体的元素，以及稳定熔融合金的过冷状态并延迟晶相结晶的元素，并且由以下组成：精细的非晶相和铝结晶相或铝过饱和固溶相，或仅为非晶相的单相。

9. 发明授权

US07528327B2 Inspection method and semiconductor device 有权
标题翻译：检验方法和半导体器件
公开(公告)号：US07528327B2
公开(公告)日：2009-05-05
申请号：US11411759
申请日：2006-04-25
申请人： Masashi Fujita
发明人： Masashi Fujita
IPC分类号： H05K1/16
CPC分类号： G01R31/046 , H05K1/0268 , H05K3/361
摘要： It is an object to provide an inspection method to enable simple and easy inspection of the electrical connecting state between a connecting terminal of a semiconductor integrated circuit over a substrate such as a glass substrate or a plastic substrate and a crimp connecting terminal of a flexible printed circuit. A crimp inspection terminal is provided to a flexible printed circuit so as to inspect all connecting terminals of the semiconductor integrated circuit over the substrate. A crimp connecting terminal and a crimp inspection terminal are connected with one connecting terminal of the semiconductor integrated circuit by thermocompression. By such a configuration, the inspection of the electrical connecting state between the connecting terminal and the crimp inspection terminal, in the other words, the inspection of conducting state can be performed by using only an external connecting terminal of the flexible printed circuit through the crimp inspection terminal.
摘要翻译：本发明的目的是提供一种检查方法，以便简单且容易地检查半导体集成电路的连接端子（例如玻璃基板或塑料基板）之间的电连接状态以及柔性印刷的压接连接端子电路。将压接检查端子设置在柔性印刷电路上，以便检查半导体集成电路在衬底上的所有连接端子。压接连接端子和压接检查端子通过热压连接到半导体集成电路的一个连接端子。通过这样的结构，可以通过仅使用柔性印刷电路的外部连接端子通过卷曲来进行对连接端子和压接检查端子之间的电连接状态的检查，换句话说，导电状态的检查检验终端。

10. 发明申请

US20090003051A1 Semiconductor Memory Device and Semiconductor Device 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20090003051A1
公开(公告)日：2009-01-01
申请号：US12144032
申请日：2008-06-23
申请人： Masashi Fujita
发明人： Masashi Fujita
IPC分类号： G11C11/34 , G11C7/00 , G11C5/14
CPC分类号： G11C15/04 , G06F12/0891 , G11C7/20 , H01L27/1108 , H01L27/12
摘要： The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor
摘要翻译：半导体存储器件包括：初始化存储单元，具有包括第一晶体管和第二晶体管的第一反相器电路;以及第二反相器电路，其输入部分连接到第一反相器电路的输出部分，输出部分连接到输入端第一反相器电路的一部分，并且包括第三晶体管和第四晶体管。第三晶体管的阈值电压的绝对值小于第一晶体管的绝对值

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