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1. 发明授权

US5202980A Information processing system capable of readily taking over processing of a faulty processor 失效
标题翻译：信息处理系统能够通过处理不合格处理器进行准备
公开(公告)号：US5202980A
公开(公告)日：1993-04-13
申请号：US547005
申请日：1990-07-02
申请人： Nobuki Morita , Shinichi Nomiyama , Kazuhito Koguchi , Yoshiaki Sugiyama
发明人： Nobuki Morita , Shinichi Nomiyama , Kazuhito Koguchi , Yoshiaki Sugiyama
IPC分类号： G06F11/20
CPC分类号： G06F11/2038 , G06F11/2028 , G06F11/2048
摘要： In an information processing system comprising a plurality of processor units each of which comprises a memory unit, an execution processor, an information transfer unit, and a bus line connected to one another, the memory unit has a control information area and a data area for storing a control information signal and a main data signal, respectively, and a saving area for saving the main data signal which is stored as a copied signal of the data signal. When the copied signal is saved into the saving area, an information transfer unit receives, through the bus line, the main data signal which is read out of the memory unit and which is transferred to the other processor unit. An additional data signal is produced by the other processor unit and stored through the information transfer unit into the saving area. Inasmuch as both the main and the additional data signals are stored in each processor unit, each processor can take over processing carried out in the other processor unit when the other processor unit is faulty.
摘要翻译：在包括多个处理器单元的信息处理系统中，每个处理器单元包括存储单元，执行处理器，信息传送单元和彼此连接的总线，所述存储单元具有控制信息区域和用于分别存储控制信息信号和主数据信号以及用于保存作为数据信号的复制信号存储的主数据信号的保存区域。当复制的信号被保存到保存区域中时，信息传送单元通过总线接收从存储器单元读出并被传送到另一个处理器单元的主数据信号。附加的数据信号由另一个处理器单元产生并通过信息传送单元存储到保存区域中。由于主数据信号和附加数据信号都存储在每个处理器单元中，所以当另一个处理器单元故障时，每个处理器可以接管在另一个处理器单元中执行的处理。

2. 发明授权

US06625678B1 Livelock avoidance method 失效
标题翻译：抢锁方法
公开(公告)号：US06625678B1
公开(公告)日：2003-09-23
申请号：US09710620
申请日：2000-11-09
申请人： Kazuhito Koguchi
发明人： Kazuhito Koguchi
IPC分类号： G06F13368
CPC分类号： G06F13/18 , G06F13/368
摘要： When a high-level bus converter receives a normal request from any one of a plurality of intermediate-level bus converters, the high-level bus converter converts the normal request into a retry response and sends the retry response to the intermediate-level bus converter, if a normal response buffer is busy. When the high-level bus converter receives an urgent request, the high-level bus converter sends a normal response in response to the urgent request to the intermediate-level bus converter. Each of a plurality of low-level bus converters issues a normal request, converts, when a retry response is received, the retry response into an urgent request, and reissues a request as the urgent request. When a plurality of urgent requests compete with each other for being processed, each of the plurality of intermediate-level bus converters arbitrates among the plurality of urgent requests, and directly transfers a winner urgent request to the high-level bus converter. Each of the plurality of intermediate-level bus converters converts at least one looser urgent request into a normal request and transfers the normal request to the high-level bus converter.
摘要翻译：当高级总线转换器接收到来自多个中间级总线转换器中的任一个的正常请求时，高级总线转换器将正常请求转换为重试响应，并将重试响应发送到中间级总线转换器如果正常响应缓冲区正忙。当高级总线转换器接收到紧急请求时，高电平总线转换器响应于对中间级总线转换器的紧急请求发送正常响应。多个低级总线转换器中的每一个发出正常请求，当接收到重试响应时将重试响应转换成紧急请求，并将请求重新发送为紧急请求。当多个紧急请求相互竞争进行处理时，多个中间级总线转换器中的每一个在多个紧急请求中进行仲裁，并直接将优胜者紧急请求传送给高级总线转换器。多个中间级总线转换器中的每一个将至少一个较松散的紧急请求转换为正常请求，并将正常请求传送到高级总线转换器。

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