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1. 发明授权

US07043717B2 Debugging apparatus and method 有权
公开(公告)号：US07043717B2
公开(公告)日：2006-05-09
申请号：US10208839
申请日：2002-08-01
申请人： Nobu Matsumoto , Takashi Miura
发明人： Nobu Matsumoto , Takashi Miura
IPC分类号： G06F9/44
CPC分类号： G06F11/3648
摘要： A first storage device stores a plurality of program codes. Each program code has an identifier. A second storage device has at least one storage area, which stores a program code to be executed of the plurality of program codes stored in the first storage device. A first variable storage area holds the identifier of the program code stored in the second storage device. A controller breaks execution of the program code when the contents of a command match those of the first variable storage area.

2. 发明授权

US5745374A Layout method for semiconductor integrated circuit and layout apparatus for semiconductor integrated circuit 失效
标题翻译：半导体集成电路布图方法及半导体集成电路布图装置
公开(公告)号：US5745374A
公开(公告)日：1998-04-28
申请号：US505735
申请日：1995-07-21
申请人： Nobu Matsumoto
发明人： Nobu Matsumoto
IPC分类号： H01L21/82 , G06F17/50 , H01L27/02 , H01L21/60 , H01L21/74
CPC分类号： G06F17/5068 , H01L27/0207
摘要： There is disclosed a layout method for a semiconductor integrated circuit for use in design by a symbolic layout which expresses a configuration of the semiconductor integrated circuit by symbols. The layout method comprises the steps of extracting a mask layout to be processed, changing dimensions of a symbolic layout included in the mask layout, replacing transistor symbols included in the mask layout with symbols having diffusion layer terminals each having a constant length in the channel width direction and not having extent in the channel length direction, shortening a length of wiring included in the mask layout in the channel width direction of the transistor, and compacting the mask layout in the channel length direction of the transistor.
摘要翻译：公开了通过符号布局在设计中使用的半导体集成电路的布局方法，其通过符号表示半导体集成电路的配置。布局方法包括以下步骤：提取要处理的掩模布局，改变包括在掩模布局中的符号布局的尺寸，用掩模布局中包括的晶体管符号代替具有扩散层端子的符号，每个扩散层端子在沟道宽度中具有恒定的长度方向而不具有通道长度方向的范围，缩短了晶体管的通道宽度方向上包括在掩模布局中的布线的长度，并且在晶体管的沟道长度方向压实掩模布局。

3. 发明授权

US07168060B2 Method of generating development environment for developing system LSI and medium which stores program therefor using VLIW designating description 失效
标题翻译：用于开发系统LSI的开发环境的生成方法和使用VLIW指定描述存储其程序的介质
公开(公告)号：US07168060B2
公开(公告)日：2007-01-23
申请号：US10197891
申请日：2002-07-19
申请人： Nobu Matsumoto , Ryuichiro Ohyama , Katsuya Uchida
发明人： Nobu Matsumoto , Ryuichiro Ohyama , Katsuya Uchida
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions.
摘要翻译：系统LSI开发环境生成方法包括从配置指定文件生成编译器的编译器定制部分，生成汇编器的汇编器定制部分，以及生成模拟器的模拟器生成部。配置指定文件包含执行指令的硬件的指定。

4. 发明申请

US20060195828A1 Instruction generator, method for generating instructions and computer program product that executes an application for an instruction generator 审中-公开
标题翻译：指令生成器，用于生成指令的方法和执行指令生成器的应用的计算机程序产品
公开(公告)号：US20060195828A1
公开(公告)日：2006-08-31
申请号：US11362125
申请日：2006-02-27
申请人： Hiroaki Nishi , Nobu Matsumoto , Yutaka Ota
发明人： Hiroaki Nishi , Nobu Matsumoto , Yutaka Ota
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： An instruction generator comprising a storage device configured to store a machine instruction function incorporating both an operation definition defining a program description in a source program targeted for substitution to a SIMD instruction, and the SIMD instruction. A parallelism analyzer is configured to analyze the source program so as to detect operators applicable to parallel execution, and to generate parallelism information indicating the set of operators applicable to parallel execution. A SIMD instruction generator is configured to perform a matching determination between an instruction generating rule for the SIMD instruction and the parallelism information, and to read the machine instruction function out of the storage device in accordance with a result of the matching determination.
摘要翻译：一种指令生成器，包括：存储装置，被配置为存储机器指令功能，该机器指令功能将定义了用于代替SIMD指令的源程序中的程序描述的操作定义与SIMD指令相结合。并行度分析器被配置为分析源程序以便检测适用于并行执行的操作符，并且生成指示适用于并行执行的操作符集的并行信息。 SIMD指令生成器被配置为在SIMD指令的指令生成规则和并行信息之间执行匹配确定，并且根据匹配确定的结果从存储装置读取机器指令功能。

5. 发明申请

US20090138862A1 PROGRAM PARALLELIZATION SUPPORTING APPARATUS AND PROGRAM PARALLELIZATION SUPPORTING METHOD 审中-公开
标题翻译：支持方案的程序并行化和程序并行化支持方法
公开(公告)号：US20090138862A1
公开(公告)日：2009-05-28
申请号：US12211420
申请日：2008-09-16
申请人： Ken Tanabe , Yutaka Ota , Nobu Matsumoto
发明人： Ken Tanabe , Yutaka Ota , Nobu Matsumoto
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A program parallelization supporting apparatus determines a determinacy in at least one dependency relationship of a data dependency, a control dependency and a pointer dependency in a program, extracts a critical path in the program, and extracts a processing instruction which exists on the critical path and has a non-deterministic determinacy in the dependency relationship. Furthermore, if a process related to a path of the extracted non-deterministic processing instruction is parallelized and the path of the non-deterministic processing instruction is deleted, the program parallelization supporting apparatus outputs parallelization labor hour information depending on the number of dependency relationships disturbing the parallelization and parallelization effect information depending on the number of processing instructions which are shortened by the parallelization.
摘要翻译：程序并行化支持装置确定程序中数据依赖性，控制依赖性和指针相关性的至少一个依赖关系的确定性，提取程序中的关键路径，并提取存在于关键路径上的处理指令，在依赖关系中具有非确定性的确定性。此外，如果与所提取的非确定性处理指令的路径相关的处理被并行并且删除非确定性处理指令的路径，则程序并行化支持装置根据依赖关系的数量来输出并行劳动时间信息并行化和并行效应信息取决于通过并行化缩短的处理指令的数量。

6. 发明申请

US20070061763A1 METHOD OF GENERATING DEVELOPMENT ENVIRONMENT FOR DEVELOPING SYSTEM LSI AND MEDIUM WHICH STORES PROGRAM THEREFOR 审中-公开
标题翻译：产生开发系统LSI的开发环境的方法及其存储程序的媒体
公开(公告)号：US20070061763A1
公开(公告)日：2007-03-15
申请号：US11556817
申请日：2006-11-06
申请人： Nobu Matsumoto , Ryuichiro Ohyama , Katsuya Uchida
发明人： Nobu Matsumoto , Ryuichiro Ohyama , Katsuya Uchida
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A system LSI development environment generating method includes a compiler customizing section which generates a compiler from a configuration designation file, an assembler customizing section which generates an assembler, and a simulator generating section which generates a simulator. The configuration designation file contains a designation of hardware which executes instructions.
摘要翻译：系统LSI开发环境生成方法包括从配置指定文件生成编译器的编译器定制部分，生成汇编器的汇编器定制部分，以及生成模拟器的模拟器生成部。配置指定文件包含执行指令的硬件的指定。

7. 发明授权

US5493509A Method of and apparatus for generating mask layouts 失效
标题翻译：用于生成蒙版布局的方法和设备
公开(公告)号：US5493509A
公开(公告)日：1996-02-20
申请号：US115144
申请日：1993-09-02
申请人： Nobu Matsumoto , Shojiro Mori
发明人： Nobu Matsumoto , Shojiro Mori
IPC分类号： G03F1/70 , G06F17/50 , H01L21/027
CPC分类号： G06F17/5081
摘要： In graphic data representing a symbolic layout for a semiconductor integrated circuit, a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles are set. First, the graphic data is cut along said first cutting lines to produce a plurality of first segment data items. These first segment data items are each compacted in the direction of the second cutting line. These compacted first segment data items are connected according to the first cutting lines. This connected first segment data is cut along the second cutting lines to produce a plurality of second segment data items. These second segment data items are each compacted in the direction of the first cutting line. These compacted second segment data items are connected to one another to produce a compacted mask layout.
摘要翻译：在表示半导体集成电路的符号布局的图形数据中，设置多个第一切割线和与第一切割线成直角交叉的多个第二切割线。首先，沿着所述第一切割线切割图形数据以产生多个第一段数据项。这些第一段数据项目在第二切割线的方向上都被压实。这些压实的第一段数据项根据第一切割线连接。该连接的第一段数据沿着第二切割线切割以产生多个第二段数据项。这些第二段数据项目在第一切割线的方向上都被压实。这些压实的第二段数据项彼此连接以产生压实的掩模布局。

8. 发明授权

US5990706A Logic circuit and method of designing the same 失效
标题翻译：逻辑电路及其设计方法
公开(公告)号：US5990706A
公开(公告)日：1999-11-23
申请号：US827506
申请日：1997-03-28
申请人： Nobu Matsumoto , Kimiyoshi Usami , Jun-ichi Tsujimoto
发明人： Nobu Matsumoto , Kimiyoshi Usami , Jun-ichi Tsujimoto
IPC分类号： H03K19/00 , G06F17/50 , H03K19/096
CPC分类号： H03K19/0963
摘要： A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).
摘要翻译： CMOS逻辑电路由用作逻辑门1的多米诺骨门组成，不配置在关键路径上并在较低电源电压（VDDL）上运行，另一个多米诺骨门用作在较高电源电压（VDDH）上工作的逻辑门2，。逻辑门1的输出是逻辑门2的输入。在逻辑门1和2之间没有配置电平转换器，因此CMOS逻辑电路的功耗很小。 CMOS逻辑电路根据满足定时要求并最大化在较低电源电压（VDDL）上工作的逻辑门数量的方法进行设计。

9. 发明授权

US5610831A Semiconductor element layout method employing process migration 失效
标题翻译：采用过程迁移的半导体元件布局方法
公开(公告)号：US5610831A
公开(公告)日：1997-03-11
申请号：US334064
申请日：1994-11-04
申请人： Nobu Matsumoto
发明人： Nobu Matsumoto
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04 , G06F15/00 , G03F9/00 , H01L21/70
CPC分类号： G06F17/5081
摘要： A semiconductor element layout method carries out process migration to convert a first mask layout prepared for integrated circuits according to a first design rule into a second mask layout that follows a second design rule. The process migration selectively removes substrate contacts that are present between adjacent elements on the first mask layout.
摘要翻译：半导体元件布局方法执行处理迁移以将根据第一设计规则为集成电路准备的第一掩模布局转换成遵循第二设计规则的第二掩模布局。过程迁移选择性地去除存在于第一掩模布局上的相邻元件之间的衬底接触。

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