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    • 10. 发明授权
    • Method and system for hybrid mapping of objects into a relational data base to provide high-speed performance and update flexibility
    • 用于将对象混合映射到关系数据库中以提供高速性能和更新灵活性的方法和系统
    • US06615204B1
    • 2003-09-02
    • US09541531
    • 2000-04-03
    • Satish Menon
    • Satish Menon
    • G06F1730
    • G06T1/00Y10S707/99933Y10S707/99945
    • A clock edge placement circuit for implementing source synchronous communication between integrated circuit devices. The clock edge placement circuit includes a delay line having an input to receive a clock signal from an external clock source. A corresponding output is included to provide the clock signal to external logic elements. The delay line structure adapted to add a propagation delay to the input, wherein the propagation delay is sized such that the phase of the clock signal is adjusted to control synchronous sampling by the external logic elements. The delay line is adapted to dynamically adjust the delay such that the phase of the clock signal at the output remains adjusted to control synchronous sampling by the external logic as variables affecting the phase of the clock signal change over time. A series of taps are included within the delay line. The delay line uses the series of taps to add a variable delay for adjusting the phase of the clock signal. Each tap is configured to add an incremental delay to the input to generate the variable delay.
    • 一种用于在集成电路器件之间实现源同步通信的时钟沿放置电路。 时钟沿放置电路包括具有用于从外部时钟源接收时钟信号的输入的延迟线。 包括相应的输出以向时间信号提供外部逻辑元件。 所述延迟线结构适于向所述输入添加传播延迟,其中所述传播延迟的大小被确定为使得所述时钟信号的相位被调整以控制所述外部逻辑元件的同步采样。 延迟线适于动态地调整延迟,使得输出端的时钟信号的相位保持调整,以控制外部逻辑的同步采样,作为影响时钟信号随时间变化的相位的变量。 延迟线中包含一系列抽头。 延迟线使用一系列抽头添加一个可变延迟来调整时钟信号的相位。 每个抽头配置为向输入添加增量延迟以生成可变延迟。