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1. 发明授权

US08065634B1 System and method for analyzing a nanotube logic circuit 有权
标题翻译：用于分析纳米管逻辑电路的系统和方法
公开(公告)号：US08065634B1
公开(公告)日：2011-11-22
申请号：US12240409
申请日：2008-09-29
申请人： Nishant Patil , Subhasish Mitra
发明人： Nishant Patil , Subhasish Mitra
IPC分类号： G06F17/50
CPC分类号： B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0558
摘要： A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.
摘要翻译：一种验证纳米管逻辑网络的方法。基于相应区域的导电性，将纳米管逻辑网络分成多个区域。确定了通过纳米管逻辑网络的邻接区域的潜在路径。确定每个潜在路径的布尔路径函数。如果潜在路径的布尔路径函数等同于预期的逻辑函数，则纳米管逻辑网络对不对准的碳纳米管是免疫的。

2. 发明授权

US07911234B1 Nanotube logic circuits 有权
标题翻译：纳米管逻辑电路
公开(公告)号：US07911234B1
公开(公告)日：2011-03-22
申请号：US12240365
申请日：2008-09-29
申请人： Nishant Patil , Subhasish Mitra
发明人： Nishant Patil , Subhasish Mitra
IPC分类号： H03K19/20
CPC分类号： B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0558
摘要： A logic cell that is immune to misaligned carbon nanotubes. Carbon nanotubes are positioned on a substrate. Contacts are formed on a layer of carbon nanotubes, including a first input contact, a second input contact, an output contact, a first gate region, and a second gate region. The output contact is positioned between the first input contact and the second input contact, and a cell region is provided bounded by a width of the output contact and residing between the first input contact and the second input contact. A nonconductive region is positioned in the layer of carbon nanotubes between any two or more of the plurality of contacts that, if shorted, would inhibit a logic function.
摘要翻译：对不对称的碳纳米管免疫的逻辑电池。碳纳米管位于基底上。触点形成在碳纳米管层上，包括第一输入触点，第二输入触点，输出触点，第一栅极区和第二栅极区。输出触点位于第一输入触点和第二输入触点之间，并且单元区域由输出触点的宽度限定并且位于第一输入触点和第二输入触点之间。非导电区域位于多个触点中的任何两个或更多个触点之间的碳纳米管层中，如果短路，则阻止逻辑功能。

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