专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08607083B2 Method and apparatus for interrupt power management 有权
标题翻译：中断电源管理方法和装置
公开(公告)号：US08607083B2
公开(公告)日：2013-12-10
申请号：US12752256
申请日：2010-04-01
申请人： Nikos Kaburlasos , Guy M Therien
发明人： Nikos Kaburlasos , Guy M Therien
IPC分类号： G06F1/32 , G06F1/00 , G06F15/16 , G06F9/46
CPC分类号： G06F9/4893 , G06F1/3203 , G06F2209/483 , Y02D10/24
摘要： Embodiments of a method and apparatus are described for low power operation of a multi-core processing system. An apparatus may comprise, for example, an affinitization management module operative to detect a media application operative to execute on one or more of a plurality of processor cores of a multi-core processor, dynamically select a subset of processor cores of the multi-core processor, and affinitize the media application to execute on the subset of processor cores. Other embodiments are described and claimed.
摘要翻译：对多核处理系统的低功率运行描述了一种方法和装置的实施例。一种装置可以包括例如可以操作以检测可操作以在多核处理器的多个处理器核的一个或多个上执行的媒体应用的亲和化管理模块，动态地选择多核处理器核心的子集处理器，并且关联媒体应用程序以在处理器核心的子集上执行。描述和要求保护其他实施例。

2. 发明申请

US20110246804A1 METHOD AND APPARATUS FOR INTERRUPT POWER MANAGEMENT 有权
标题翻译：中断电源管理的方法和装置
公开(公告)号：US20110246804A1
公开(公告)日：2011-10-06
申请号：US12752256
申请日：2010-04-01
申请人： Nikos Kaburlasos , Guy M. Therien
发明人： Nikos Kaburlasos , Guy M. Therien
IPC分类号： G06F9/46 , G06F1/28 , G06F3/14
CPC分类号： G06F9/4893 , G06F1/3203 , G06F2209/483 , Y02D10/24
摘要： Embodiments of a method and apparatus are described for low power operation of a multi-core processing system. An apparatus may comprise, for example, an affinitization management module operative to detect a media application operative to execute on one or more of a plurality of processor cores of a multi-core processor, dynamically select a subset of processor cores of the multi-core processor, and affinitize the media application to execute on the subset of processor cores. Other embodiments are described and claimed.
摘要翻译：对多核处理系统的低功率运行描述了一种方法和装置的实施例。一种装置可以包括例如可以操作以检测可操作以在多核处理器的多个处理器核的一个或多个上执行的媒体应用的亲和化管理模块，动态地选择多核处理器核心的子集处理器，并且关联媒体应用程序以在处理器核心的子集上执行。描述和要求保护其他实施例。

3. 发明授权

US10025367B2 Dynamic scaling of graphics processor execution resources 有权
公开(公告)号：US10025367B2
公开(公告)日：2018-07-17
申请号：US14463573
申请日：2014-08-19
申请人： Nikos Kaburlasos , Eric Samson
发明人： Nikos Kaburlasos , Eric Samson
IPC分类号： G06F1/32
摘要： In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

4. 发明授权

US08209480B2 DRAM selective self refresh 有权
标题翻译： DRAM选择性自刷新
公开(公告)号：US08209480B2
公开(公告)日：2012-06-26
申请号：US12835525
申请日：2010-07-13
申请人： Nikos Kaburlasos , Jim Kardaeh
发明人： Nikos Kaburlasos , Jim Kardaeh
IPC分类号： G06F12/02
CPC分类号： G06F12/0292 , G11C11/406 , G11C11/40615 , G11C2211/4067 , Y02D10/13
摘要： In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.
摘要翻译：在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑，在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。可以描述其他实施例。

5. 发明授权

US08095725B2 Device, system, and method of memory allocation 有权
标题翻译：设备，系统和内存分配方法
公开(公告)号：US08095725B2
公开(公告)日：2012-01-10
申请号：US11967296
申请日：2007-12-31
申请人： Jim Kardach , Nikos Kaburlasos
发明人： Jim Kardach , Nikos Kaburlasos
IPC分类号： G06F12/02
CPC分类号： G11C11/40618 , G06F12/0223 , G06F12/06 , G06F12/0607 , G06F2212/1028 , G11C7/1072 , G11C11/406 , G11C11/40622 , Y02D10/13
摘要： Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.
摘要翻译：设备，系统和内存分配方法。例如，一种装置包括：包括存储数据的多个动态随机存取存储器（DRAM）单元的双列直插存储器模块（DIMM），其中每个DRAM单元包括多个存储体，并且每个存储体被分成多个的子银行; 以及存储器管理单元，用于将所述DIMM的交织子组的一组分配给操作系统的存储器页，其中所述交织子组的组合存储器大小等于所述存储器页的大小操作系统。

6. 发明授权

US07757039B2 DRAM selective self refresh 有权
标题翻译： DRAM选择性自刷新
公开(公告)号：US07757039B2
公开(公告)日：2010-07-13
申请号：US11901502
申请日：2007-09-18
申请人： Nikos Kaburlasos , Jim Kardach
发明人： Nikos Kaburlasos , Jim Kardach
IPC分类号： G06F12/02 , G06F1/32
CPC分类号： G06F12/0292 , G11C11/406 , G11C11/40615 , G11C2211/4067 , Y02D10/13
摘要： In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.
摘要翻译：在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑，在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。可以描述其他实施例。

7. 发明授权

US07478214B2 Clock-gated random access memory 有权
标题翻译：时钟门控随机存取存储器
公开(公告)号：US07478214B2
公开(公告)日：2009-01-13
申请号：US11325887
申请日：2006-01-04
申请人： Nikos Kaburlasos
发明人： Nikos Kaburlasos
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A method and apparatus for gating a clock signal to one or more embedded blocks of a random access memory (RAM), is described. In one embodiment, a clock gating block is coupled to a RAM EBB, the clock-gating block to provide a RAM clock when receiving read and write enable signals and to provide a gated clock signal when the RAM EBB is idle. In another embodiment, a clock gating block is coupled to a RAM bank, having a plurality of RAM EBBs, the clock-gating block to provide a RAM clock to the RAM bank when receiving read and write enable signals and to provide a gated clock signal to the RAM bank when the RAM bank is idle.
摘要翻译：描述了用于将时钟信号选通到随机存取存储器（RAM）的一个或多个嵌入块的方法和装置。在一个实施例中，时钟门控模块耦合到RAM EBB，时钟门控模块，当接收到读和写使能信号时提供RAM时钟，并在RAM EBB空闲时提供选通时钟信号。在另一个实施例中，时钟门控模块耦合到具有多个RAM EBB的RAM存储体，时钟门控模块在接收到读和写使能信号时向RAM存储体提供RAM时钟，并提供门控时钟信号到RAM存储区时，RAM存储空闲。

8. 发明申请

US20180300238A1 ADAPTIVE CACHE SIZING PER WORKLOAD 审中-公开
公开(公告)号：US20180300238A1
公开(公告)日：2018-10-18
申请号：US15488637
申请日：2017-04-17
申请人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Balaji Vembu , Altug Koker , Josh B. Mastronarde , Nikos Kaburlasos , Abhishek R. Appu , Sanjeev S. Jahagirdar , Eric J. Asperheim , Subramaniam Maiyuran , Kiran C. Veernapu , Pattabhiraman K , Kamal Sinha , Bhushan M. Borole , Wenyin Fu , Joydeep Ray , Prasoonkumar Surti , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F12/06
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

9. 发明申请

US20160093013A1 Reconfigurable Graphics Processor for Performance Improvement 审中-公开
公开(公告)号：US20160093013A1
公开(公告)日：2016-03-31
申请号：US14959455
申请日：2015-12-04
申请人： Nikos Kaburlasos , Eric C. Samson
发明人： Nikos Kaburlasos , Eric C. Samson
IPC分类号： G06T1/20 , G09G5/36 , G06F1/32
CPC分类号： G09G5/36 , G06F1/26 , G06F1/3203 , G06F1/3265 , G06F1/329 , G09G5/363 , G09G2330/021 , G09G2360/06 , G09G2360/08 , Y02D10/153 , Y02D10/24 , Y02D50/20
摘要： Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.

10. 发明申请

US20150035853A1 Partial Tile Rendering 有权
公开(公告)号：US20150035853A1
公开(公告)日：2015-02-05
申请号：US13955228
申请日：2013-07-31
申请人： Nikos Kaburlasos , Eric C. Samson , Robert B. Taylor
发明人： Nikos Kaburlasos , Eric C. Samson , Robert B. Taylor
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06T1/00 , G06T1/60 , G09G5/001 , G09G5/363 , G09G5/395 , G09G2330/021 , G09G2360/08 , G09G2360/122 , G09G2360/18
摘要： In accordance with some embodiments, partial rendering of non-changing or slowly changing frame tiles allows the graphics processing unit to spend less time processing non-changing or slowly changing portions of each frame, saving power and creating more room for performance in some embodiments.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式