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1. 发明授权

US09628095B1 Parameterizable method for simulating PLL behavior 有权
公开(公告)号：US09628095B1
公开(公告)日：2017-04-18
申请号：US13604577
申请日：2012-09-05
申请人： Nikolaos Liveris , Kevin W. Mai , Jakob Jones , Yury Markovskiy , Jeffrey Fox
发明人： Nikolaos Liveris , Kevin W. Mai , Jakob Jones , Yury Markovskiy , Jeffrey Fox
IPC分类号： G06F17/50 , H03L7/14
CPC分类号： H03L7/145 , H03L7/18
摘要： Methods for designing and developing models for simulating the behavior of clock signals and in particular those generated by phase-locked loop (PLL) circuits are provided. The clock period of a phase-locked loop circuit's variable frequency oscillator signal may be modeled by combining the inverse of the oscillator frequency rounded up to the simulation time scale with the inverse rounded down to the simulation time scale. The variable frequency oscillator signal may further be synchronized with a reference clock signal at a rate determined by the relationship between the reference clock signal and the variable frequency oscillator signal. A parameter may indicate a target range for the deviation between the two signals and a runtime monitor may be used together with the parameter setting to decide whether synchronization is required and make the appropriate adjustments.

2. 发明授权

US07631211B1 Sharing elements in multiple data-rate I/O 有权
标题翻译：在多个数据速率I / O中共享元素
公开(公告)号：US07631211B1
公开(公告)日：2009-12-08
申请号：US11476341
申请日：2006-06-27
申请人： Kevin W. Mai
发明人： Kevin W. Mai
IPC分类号： G06F1/00
CPC分类号： G06F1/08 , G11C8/18
摘要： Circuits, methods, and apparatus are directed to sharing input and output functionality. A timing circuit usable for input and output functionality may be combined with another timing circuit to provide additional input/output functionality or to reduce the number of circuit elements for input/output functionality. For example, two timing circuits may be used to provide double data-rate input while still providing output functionality, or vice versa. Two timing circuits may also provide output that is timed and gated with an output enable signal.
摘要翻译：电路，方法和装置旨在共享输入和输出功能。可用于输入和输出功能的定时电路可以与另一个定时电路组合以提供额外的输入/输出功能或减少用于输入/输出功能的电路元件的数量。例如，可以使用两个定时电路来提供双数据速率输入，同时仍然提供输出功能，反之亦然。两个定时电路还可以提供定时和门控输出使能信号的输出。

3. 发明授权

US5767922A Apparatus and process for detecting scene breaks in a sequence of video frames 失效
标题翻译：用于检测视频帧序列中的场景中断的设备和过程
公开(公告)号：US5767922A
公开(公告)日：1998-06-16
申请号：US628374
申请日：1996-04-05
申请人： Ramin Zabih , Justin F. Miller , Kevin W. Mai
发明人： Ramin Zabih , Justin F. Miller , Kevin W. Mai
IPC分类号： H04N5/14
CPC分类号： G06K9/00711 , H04N5/147
摘要： Apparatus and process for detecting scene breaks in a sequence of video frames providing a moving picture. Entering and exiting edge pixels in each of a plurality of successive video frames are counted, and an edge change fraction for each of the successive video frames is derived therefrom. Peaks which are detected in the edge change fractions are indicative of scene breaks.
摘要翻译：用于检测提供运动图像的视频帧序列中的场景中断的装置和过程。对多个连续视频帧中的每一个中进入和退出边缘像素进行计数，并从其中导出每个连续视频帧的边缘变化分数。在边缘变化分数中检测到的峰表示场景中断。

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