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1. 发明授权

US08121573B2 Method and system for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops 有权
标题翻译：一种利用多个锁相环的多频段多标准通信系统中共存的方法和系统
公开(公告)号：US08121573B2
公开(公告)日：2012-02-21
申请号：US12325750
申请日：2008-12-01
申请人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
发明人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04B15/06 , H03L7/18 , H04B1/0475
摘要： Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.
摘要翻译：公开了利用多个锁相环（PLL）的多频带多标准通信系统中共存的方法和系统。方面可以包括确定收发器的一个或多个期望的操作频率，确定不想要的信号的频率，例如杂散，互调和/或混合乘积信号，以及配置PLL以期望频率的倍数工作，同时避免不需要的信号。期望的频率可以利用整数产生，其可以包括多模式分频器。无线标准可以包括例如LTE，GSM，EDGE，GPS，蓝牙，WiFi和/或WCDMA。频率可以被配置为减轻干扰。在TDD模式下工作时可以共享PLL，并在FDD模式下单独使用。可以利用PLL来产生一个或多个数字接口信号，发射器支线发射掩模上的零异常以及收发器中的ADC和/或DAC的采样时钟。

2. 发明授权

US09148233B2 Method and system for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops 有权
标题翻译：一种利用多个锁相环的多频段多标准通信系统中共存的方法和系统
公开(公告)号：US09148233B2
公开(公告)日：2015-09-29
申请号：US13614113
申请日：2012-09-13
申请人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
发明人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
IPC分类号： H03L7/18 , H04B15/06 , H04B1/04
CPC分类号： H04B15/06 , H03L7/18 , H04B1/0475
摘要： Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the Plls to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCOMA, for example. The frequencies may be configured to mitigate interference. Plls may be shared when operating in TOO mode, and used separately operating in FOO mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for AOCs and/or DACs in the transceiver may be generated utilizing the PLLs.
摘要翻译：公开了利用多个锁相环（PLL）的多频带多标准通信系统中共存的方法和系统。方面可以包括确定收发器的一个或多个期望的操作频率，确定不想要的信号的频率，例如杂散，互调和/或混合乘积信号，以及将Pll设置为以期望频率的倍数工作，同时避免不需要的信号。期望的频率可以利用整数产生，其可以包括多模式分频器。无线标准可以包括例如LTE，GSM，EDGE，GPS，蓝牙，WiFi和/或WCOMA。频率可以被配置为减轻干扰。在TOO模式下可以共享Pll，并在FOO模式下单独使用。利用PLL可以生成一个或多个数字接口信号，发射器支线发射掩模上的零异常以及收发器中的AOC和/或DAC的采样时钟。

3. 发明申请

US20120236766A1 Method and System for Coexistence in a Multiband, Multistandard Communication System Utilizing a Plurality of Phase Locked Loops 有权
标题翻译：使用多个锁相环的多频段，多标准通信系统中共存的方法和系统
公开(公告)号：US20120236766A1
公开(公告)日：2012-09-20
申请号：US13399557
申请日：2012-02-17
申请人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
发明人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
IPC分类号： H04B15/00 , H04J3/00 , H04J1/00 , H04B1/40
CPC分类号： H04B15/06 , H03L7/18 , H04B1/0475
摘要： Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.
摘要翻译：公开了利用多个锁相环（PLL）的多频带多标准通信系统中共存的方法和系统。方面可以包括确定收发器的一个或多个期望的操作频率，确定不想要的信号的频率，例如杂散，互调和/或混合乘积信号，以及配置PLL以期望频率的倍数工作，同时避免不需要的信号。期望的频率可以利用整数产生，其可以包括多模式分频器。无线标准可以包括例如LTE，GSM，EDGE，GPS，蓝牙，WiFi和/或WCDMA。频率可以被配置为减轻干扰。在TDD模式下工作时可以共享PLL，并在FDD模式下单独使用。可以利用PLL来产生一个或多个数字接口信号，发射器支线发射掩模上的零异常以及收发器中的ADC和/或DAC的采样时钟。

4. 发明授权

US08581362B2 Wireless communication devices with in-package integrated passive components 有权
标题翻译：带有封装内集成无源元件的无线通信设备
公开(公告)号：US08581362B2
公开(公告)日：2013-11-12
申请号：US13409973
申请日：2012-03-01
申请人： Nikolaos Haralabidis , Konstantinos Vavelidis , Kosmas-Christos Tsilipanos
发明人： Nikolaos Haralabidis , Konstantinos Vavelidis , Kosmas-Christos Tsilipanos
IPC分类号： H01L23/522
CPC分类号： H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/66 , H01L2223/6644 , H01L2223/6655 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure can be used to both reduce the size and cost and improve the performance and power consumption of next generation wireless communication devices. In particular, embodiments enable board and semiconductor substrate area savings by using the fabrication package (which encapsulates the semiconductor substrate) as a design element in the design of next generation wireless communication devices. Specifically, embodiments use the substrate of the fabrication package to integrate into it components of the wireless radio transceiver (which are conventionally integrated into the semiconductor substrate) and other discrete components of the communication device (which are conventionally placed on the board of the device). As such, reduced board and semiconductor area can be realized.
摘要翻译：本公开的实施例可以用于减小下一代无线通信设备的尺寸和成本并提高其性能和功耗。具体地，实施例通过使用制造封装（其封装半导体衬底）作为下一代无线通信设备的设计中的设计元件来实现板和半导体衬底面积的节省。具体地，实施例使用制造封装的基板将无线无线电收发器（其通常集成到半导体基板中）和通信设备的其它分立部件（其通常放置在设备的板上）的部件集成到其中，。因此，可以实现减少的板和半导体面积。

5. 发明授权

US08346196B2 Method and system for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops 有权
标题翻译：一种利用多个锁相环的多频段多标准通信系统中共存的方法和系统
公开(公告)号：US08346196B2
公开(公告)日：2013-01-01
申请号：US13399557
申请日：2012-02-17
申请人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
发明人： Nikolaos Haralabidis , Ioannis Kokolakis , Nikolaos Kanakaris , Konstantinos Vavelidis
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H04B15/06 , H03L7/18 , H04B1/0475
摘要： Methods and systems for coexistence in a multiband, multistandard communication system utilizing a plurality of phase locked loops (PLLs) are disclosed. Aspects may include determining one or more desired frequencies of operation of a transceiver, determining a frequency of unwanted signals such as spurs, intermodulation, and/or mixing product signals, and configuring the PLLs to operate at a multiple of the desired frequencies while avoiding the unwanted signals. The desired frequencies may be generated utilizing integer, which may include multi-modulus dividers. The wireless standards may include LTE, GSM, EDGE, GPS, Bluetooth, WiFi, and/or WCDMA, for example. The frequencies may be configured to mitigate interference. PLLs may be shared when operating in TDD mode, and used separately operating in FDD mode. One or more digital interface signals, zero exceptions on a transmitter spur emission mask, and sampling clocks for ADCs and/or DACs in the transceiver may be generated utilizing the PLLs.
摘要翻译：公开了利用多个锁相环（PLL）的多频带多标准通信系统中共存的方法和系统。方面可以包括确定收发器的一个或多个期望的操作频率，确定不想要的信号的频率，例如杂散，互调和/或混合乘积信号，以及配置PLL以期望频率的倍数工作，同时避免不需要的信号。期望的频率可以利用整数产生，其可以包括多模式分频器。无线标准可以包括例如LTE，GSM，EDGE，GPS，蓝牙，WiFi和/或WCDMA。频率可以被配置为减轻干扰。在TDD模式下工作时可以共享PLL，并在FDD模式下单独使用。可以利用PLL来产生一个或多个数字接口信号，发射器支线发射掩模上的零异常以及收发器中的ADC和/或DAC的采样时钟。

6. 发明申请

US20070207760A1 Method and system for filter calibration using fractional-N frequency synthesized signals 失效
$Method and system for filter calibration using fractional-N frequency synthesized signals$
标题翻译：使用分数N频率合成信号进行滤波校准的方法和系统
公开(公告)号：US20070207760A1
公开(公告)日：2007-09-06
申请号：US11431960
申请日：2006-05-11
申请人： Spyridon Kavadias , Konstantinos Vavelidis , Nikolaos Haralabidis
发明人： Spyridon Kavadias , Konstantinos Vavelidis , Nikolaos Haralabidis
IPC分类号： H04B1/40 , H04B1/06
CPC分类号： H04B1/30 , H04B1/405 , H04H60/91
摘要： A method and system for filter calibration using fractional-N frequency synthesized signals are presented. Aspects of the method may include generating an LO signal by a PLL circuit within a chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. A frequency response for a filter circuit integrated within the chip may be calibrated by adjusting parameters associated with the filter circuit based on the generated LO signal. Aspects of the system may include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The frequency response may be calibrated by adjusting the filter based on the generated reference signal.
摘要翻译：提出了使用分数N频率合成信号进行滤波校准的方法和系统。该方法的方面可以包括通过芯片内的PLL电路生成LO信号。可以基于所生成的LO信号和合成器控制信号来生成参考信号。集成在芯片内的滤波器电路的频率响应可以通过基于产生的LO信号调整与滤波器电路相关联的参数来校准。系统的方面可以包括单芯片多频带RF接收机，其能够通过单芯片内的PLL电路产生LO信号，并且能够校准集成在芯片内的滤波器电路的频率响应。可以基于所生成的LO信号和合成器控制信号来生成参考信号。可以通过基于产生的参考信号调整滤波器来校准频率响应。

7. 发明申请

US20070066272A1 Method and system for multi-band direct conversion CMOS mobile television tuner 有权
标题翻译：多频直接转换CMOS手机电视调谐器的方法与系统
公开(公告)号：US20070066272A1
公开(公告)日：2007-03-22
申请号：US11385390
申请日：2006-03-21
申请人： Iason Vassiliou , Konstantinos Vavelidis , Stamatios Bouras , Spyridon Kavadias , Ioannis Kokolakis , Georgios Kamoulakos , Aristeidis Kyranas , Charalampos Kapnistis , Nikolaos Haralabidis
发明人： Iason Vassiliou , Konstantinos Vavelidis , Stamatios Bouras , Spyridon Kavadias , Ioannis Kokolakis , Georgios Kamoulakos , Aristeidis Kyranas , Charalampos Kapnistis , Nikolaos Haralabidis
IPC分类号： H04B7/08 , H04B1/18
CPC分类号： H04B1/0064
摘要： Aspects of a method and system for a multi-band direct conversion CMOS mobile television tuner are provided. A single-chip multi-band RF receiver in a mobile terminal comprising UHF and L-band front-ends receives and amplifies an RF signal utilizing an LNA integrated into the front-end that corresponds to the type of signal received. A received signal strength indicator (RSSI) value may be determined for the amplified signal within the single-chip receiver and may be utilized to adjust a gain of the LNA. The adjustment may be made via on-chip or off-chip processing of the RSSI value. The single-chip receiver may directly convert the amplified signal to a baseband frequency signal and generate in-phase and quadrature components. The components of the baseband frequency signal may be filtered and/or amplified via programmable devices within the single-chip receiver. Circuitry within the single-chip receiver may be controller via an on-chip digital interface.
摘要翻译：提供了一种用于多频带直接转换CMOS移动电视调谐器的方法和系统的方面。包括UHF和L波段前端的移动终端中的单芯片多频带RF接收机使用集成到前端中的对应于所接收信号类型的LNA来接收并放大RF信号。可以针对单芯片接收机内的放大信号确定接收信号强度指示符（RSSI）值，并且可以用于调整LNA的增益。可以通过RSSI值的片上或片外处理来进行调整。单芯片接收机可以将放大的信号直接转换为基带频率信号，并产生同相和正交分量。可以通过单芯片接收机内的可编程器件对基带频率信号的分量进行滤波和/或放大。单芯片接收机内的电路可以通过片上数字接口进行控制。

8. 发明授权

US08902796B2 Power-efficient multi-mode transceiver synthesizer configurations 有权
标题翻译：功率高效的多模收发器合成器配置
公开(公告)号：US08902796B2
公开(公告)日：2014-12-02
申请号：US13432528
申请日：2012-03-28
申请人： Nikolaos Haralabidis , Konstantinos Vavelidis
发明人： Nikolaos Haralabidis , Konstantinos Vavelidis
IPC分类号： H04B7/005 , H04B1/40
CPC分类号： H04B1/403
摘要： Embodiments of the present disclosure provide power-efficient time division duplexing (TDD) mode configurations of frequency division duplexing (FDD) transceivers. Embodiments avoid time slotted operation of the receive and transmit synthesizers, thereby avoiding undesired operation under transient conditions, frequent calibration, and reduced power supply efficiency. In embodiments, a single synthesizer is used to enable TDD operation, thereby reducing power consumption and calibration requirements by approximately 50%. The single synthesizer may be maintained ON at all times, thus allowing the power supply's switching regulator to operate with substantially constant load conditions.
摘要翻译：本公开的实施例提供频分双工（FDD）收发器的功率有效的时分双工（TDD）模式配置。实施例避免接收和发射合成器的时隙操作，从而避免在瞬态条件下的不期望的操作，频繁的校准和降低的电源效率。在实施例中，使用单个合成器来实现TDD操作，从而将功耗和校准要求降低约50％。单个合成器可以始终保持接通，从而允许电源的开关调节器以基本恒定的负载条件运行。

9. 发明授权

US08755479B2 Minimization of spurs generated from a free running oscillator 有权
标题翻译：最小化自由振荡器产生的杂散
公开(公告)号：US08755479B2
公开(公告)日：2014-06-17
申请号：US13450134
申请日：2012-04-18
申请人： Konstantinos Vavelidis , Nikolaos Haralabidis
发明人： Konstantinos Vavelidis , Nikolaos Haralabidis
IPC分类号： H03D3/24
CPC分类号： H03L7/1974 , H03L7/10
摘要： Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated.
摘要翻译：本公开的实施例包括其中由自由振荡器提供的振荡信号的振荡频率漂移产生的杂散可以由锁相环（PLL）的输出信号最小化和/或消除的方法。方法包括调整自由振荡器以防止振荡频率漂移，从而消除杂散。当通信设备接合已知不产生杂散的通信信道时产生的性能数据与当通信设备接合期望的通信信道时所生成的性能数据进行比较。调整自由运行的振荡器，直到两种类型的性能数据匹配。其他方法包括调整PLL的抖动模块以防止振荡频率漂移，从而消除杂散。

10. 发明申请

US20130114771A1 Minimization of Spurs Generated from a Free Running Oscillator 有权
标题翻译：最小化自由运行振荡器产生的马刺
公开(公告)号：US20130114771A1
公开(公告)日：2013-05-09
申请号：US13450134
申请日：2012-04-18
申请人： Konstantinos Vavelidis , Nikolaos Haralabidis
发明人： Konstantinos Vavelidis , Nikolaos Haralabidis
IPC分类号： H03L7/08
CPC分类号： H03L7/1974 , H03L7/10
摘要： Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated.
摘要翻译：本公开的实施例包括其中由自由振荡器提供的振荡信号的振荡频率漂移产生的杂散可以由锁相环（PLL）的输出信号最小化和/或消除的方法。方法包括调整自由振荡器以防止振荡频率漂移，从而消除杂散。当通信设备接合已知不产生杂散的通信信道时产生的性能数据与当通信设备接合期望的通信信道时所生成的性能数据进行比较。调整自由运行的振荡器，直到两种类型的性能数据匹配。其他方法包括调整PLL的抖动模块以防止振荡频率漂移，从而消除杂散。

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