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1. 发明申请

US20080319730A1 Method and Apparatus for Modifying a Virtual Processor Model for Hardware/Software Simulation 有权
标题翻译：用于修改硬件/软件仿真的虚拟处理器模型的方法和装置
公开(公告)号：US20080319730A1
公开(公告)日：2008-12-25
申请号：US12159831
申请日：2007-07-30
申请人： Neville A. Clark , James R. Torossian
发明人： Neville A. Clark , James R. Torossian
IPC分类号： G06F15/00
CPC分类号： G06F17/5022 , G06F17/5009 , G06F2217/86
摘要： A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.
摘要翻译：将所提供的虚拟处理器模型变换为用户虚拟处理器模型的方法。还提供了一种工具，例如作为用于在主计算机系统中操作以用于将所提供的虚拟处理器模型转换为用户虚拟处理器模型的指令来提供的工具。还有一种指定目标处理器的一个或多个特征的方法，以将提供的虚拟处理器模型转换成在c仿真系统中操作时模拟目标处理器的操作的用户虚拟处理器模型。例如，指定将所提供的虚拟处理器模型转换成用户虚拟处理器模型的指令的一个或多个特性的方法。

2. 发明授权

US07567893B2 Clock simulation system and method 有权
标题翻译：时钟仿真系统及方法
公开(公告)号：US07567893B2
公开(公告)日：2009-07-28
申请号：US11315683
申请日：2005-12-20
申请人： James R. Torossian , Neville A. Clark
发明人： James R. Torossian , Neville A. Clark
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A simulation system, a computer product to implement a simulation method, and a method of simulating a digital circuit that has at least one element and at least one clock signal having clock attributes. The method includes maintaining a data structure for time-scheduled events scheduled to occur at particular simulation-times; and maintaining a data structure for clock-scheduled events each corresponding to a particular clock signal and scheduled to occur at a time that can be determined from at least one attribute of the clock signal, such that clocked-scheduled events are distinguishable from time-scheduled events, and such that each and every transition of any clock signal need not be scheduled in the time-scheduled event data structure.
摘要翻译：模拟系统，用于实现模拟方法的计算机产品，以及模拟具有至少一个元件和至少一个具有时钟属性的时钟信号的数字电路的方法。该方法包括维护调度在特定模拟时间发生的时间安排事件的数据结构; 并且保持每个对应于特定时钟信号的时钟预定事件的数据结构，并且被调度为在可以根据时钟信号的至少一个属性确定的时间发生，使得计时事件与时间调度事件，并且使得任何时钟信号的每个转换不需要在时间调度事件数据结构中调度。

3. 发明授权

US08644305B2 Method and system for modeling a bus for a system design incorporating one or more programmable processors 有权
标题翻译：用于对包含一个或多个可编程处理器的系统设计的总线进行建模的方法和系统
公开(公告)号：US08644305B2
公开(公告)日：2014-02-04
申请号：US12017939
申请日：2008-01-22
申请人： Neville A. Clark , James R. Torossian
发明人： Neville A. Clark , James R. Torossian
IPC分类号： H04L12/50 , H04J3/24 , G06F13/42
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.
摘要翻译：提供了用于为系统设计建立总线的系统和方法。在一个实施例中，该方法通过接受虚拟总线模型来操作，其中模型模拟总线主设备和从设备的行为，使得该模型精确地模拟从主设备到从设备的数据传输的定时和行为，以及从从设备到主设备。该方法将主设备发出的事务路由到从设备。交易具有用于交易数据的存储，或者是通过交易传送的交易数据的指针。交易数据在一个或多个数据有效载荷中传送，数据发送者设置要返回的数据有效载荷的长度。数据有效载荷从数据的发送者发送到数据的接收器，并且可以包含一个或多个总线数据跳动。该方法将一个或多个数据节拍的总线时序和行为精确地建模为一个数据有效载荷。

4. 发明授权

US08463589B2 Modifying a virtual processor model for hardware/software simulation 有权
公开(公告)号：US08463589B2
公开(公告)日：2013-06-11
申请号：US12159831
申请日：2007-07-30
申请人： Neville A. Clark , James R. Torossian
发明人： Neville A. Clark , James R. Torossian
IPC分类号： G06F9/45 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/5009 , G06F2217/86
摘要： A method of transforming a provided virtual processor model to a user virtual processor model. Also a tool, e.g., provided as instructions for operating in a host computer system for converting a provided virtual processor model to a user virtual processor model. Also a method of specifying one or more characteristics of a target processor to transform a provided virtual processor model to a user virtual processor model that when operating in a c-simulation system, simulates the operation of the target processor. For example, a method of specifying one or more characteristics of instructions to transform a provided virtual processor model to a user virtual processor model.

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