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1. 发明申请

US20160057081A1 PPI DE-ALLOCATE CPP BUS COMMAND 有权
标题翻译： PPI去分配CPP总线命令
公开(公告)号：US20160057081A1
公开(公告)日：2016-02-25
申请号：US14464700
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Ronald N. Fortino
IPC分类号： H04L12/935 , H04L12/863 , H04L12/947
CPC分类号： H04L49/3018 , H04L47/624 , H04L49/252
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI addressing mode in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine, and is allocated a PPI by the packet engine, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine. Once the packet portion has been processed, a PPI de-allocation command causes the packet engine to de-allocate the PPI so that the PPI is available for allocating in association with another packet portion.
摘要翻译：在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。不是将PDRSD管理分组部分存储到存储器中，而是提供分组引擎。 PDRSD使用PPI寻址模式与分组引擎进行通信，并指示分组引擎存储分组部分。 PDRSD从分组引擎请求PPI，并由分组引擎分配PPI，然后用PPI标记要写入的分组部分，并将分组部分和PPI发送到分组引擎。一旦分组部分被处理，PPI解除分配命令使分组引擎去分配PPI，使得PPI可用于与另一分组部分相关联地分配。

2. 发明授权

US09971720B1 Distributed credit FIFO link of a configurable mesh data bus 有权
公开(公告)号：US09971720B1
公开(公告)日：2018-05-15
申请号：US14724820
申请日：2015-05-29
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ronald N. Fortino
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F13/00 , H04L47/39 , H04L49/901
摘要： An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar switch and radiating half links. The half links of adjacent islands align to form links between crossbar switches. A link is implemented as two distributed credit FIFOs. In one direction, a link portion involves a FIFO associated with an output port of a first island, a first chain of registers, and a second FIFO associated with an input port of a second island. When a transaction value passes through the FIFO and through the crossbar switch of the second island, an arbiter in the crossbar switch returns a taken signal. The taken signal passes back through a second chain of registers to a credit count circuit in the first island. The credit count circuit maintains a credit count value for the distributed credit FIFO.

3. 发明申请

US20160057079A1 PPI ALLOCATION REQUEST AND RESPONSE FOR ACCESSING A MEMORY SYSTEM 有权
标题翻译： PPI分配请求和用于访问存储系统的响应
公开(公告)号：US20160057079A1
公开(公告)日：2016-02-25
申请号：US14464692
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Ronald N. Fortino
IPC分类号： H04L12/911 , H04L12/935
CPC分类号： H04L49/3072 , H04L45/742 , H04L49/9042
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine in a PPI allocation request, and is allocated a PPI by the packet engine in a PPI allocation response, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine.
摘要翻译：在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 PDRSD在与分组引擎通信并指示分组引擎存储分组部分时使用PPI（分组部分标识符）寻址模式（PAM）。 PDRSD在PPI分配请求中从分组引擎请求PPI，并且在PPI分配响应中由分组引擎分配PPI，然后标记要用PPI写入的分组部分，并发送分组部分和PPI 到包引擎。

4. 发明授权

US09940097B1 Registered FIFO 有权
公开(公告)号：US09940097B1
公开(公告)日：2018-04-10
申请号：US14527550
申请日：2014-10-29
申请人： Netronome Systems, Inc.
发明人： Ronald N. Fortino , Gavin J. Stark , Steven W. Zagorianakos
IPC分类号： G06F3/00 , G06F5/00 , G06F5/14 , H04L25/00 , G06F13/40 , G06F9/34 , H04B1/38
CPC分类号： G06F5/14 , G06F5/08 , G06F9/34 , G06F13/40 , G06F2205/126 , H04B1/38 , H04L25/00
摘要： A registered synchronous FIFO has a tail register, internal registers, and a head register. The FIFO cannot be pushed if it is full and cannot be popped if it is empty, but otherwise can be pushed and/or popped. Within the FIFO, the internal signal fanout of incoming data circuitry and push control circuitry and is minimized and remains essentially constant regardless of the number of registers of the FIFO. The output delay of the output data also is essentially constant regardless of the number of registers of the FIFO. An incoming data value can only be written into the head or tail. If a data value is in the tail and one of the internal registers is empty, and if no push or pop is to be performed in a clock cycle, then nevertheless the data value in the tail is moved into the empty internal register in the cycle.

5. 发明授权

US10911038B1 Configuration mesh data bus and transactional memories in a multi-processor integrated circuit 有权
公开(公告)号：US10911038B1
公开(公告)日：2021-02-02
申请号：US16247566
申请日：2019-01-15
申请人： Netronome Systems, Inc.
发明人： Gavin J. Stark , Steven W. Zagorianakos , Ronald N. Fortino
IPC分类号： H03K17/00 , G06F13/40 , G06F9/46
摘要： A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.

6. 发明授权

US09559988B2 PPI allocation request and response for accessing a memory system 有权
标题翻译：用于访问存储系统的PPI分配请求和响应
公开(公告)号：US09559988B2
公开(公告)日：2017-01-31
申请号：US14464692
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Ronald N. Fortino
IPC分类号： H04L12/911 , H04L12/935 , H04L12/747 , H04L12/861
CPC分类号： H04L49/3072 , H04L45/742 , H04L49/9042
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine in a PPI allocation request, and is allocated a PPI by the packet engine in a PPI allocation response, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine.
摘要翻译：在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 PDRSD在与分组引擎通信并指示分组引擎存储分组部分时使用PPI（分组部分标识符）寻址模式（PAM）。 PDRSD在PPI分配请求中从分组引擎请求PPI，并且在PPI分配响应中由分组引擎分配PPI，然后标记要用PPI写入的分组部分，并发送分组部分和PPI 到包引擎。

7. 发明授权

US09548947B2 PPI de-allocate CPP bus command 有权
标题翻译： PPI取消分配CPP总线命令
公开(公告)号：US09548947B2
公开(公告)日：2017-01-17
申请号：US14464700
申请日：2014-08-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark , Ronald N. Fortino
IPC分类号： H04L12/935 , H04L12/863 , H04L12/947
CPC分类号： H04L49/3018 , H04L47/624 , H04L49/252
摘要： Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI addressing mode in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine, and is allocated a PPI by the packet engine, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine. Once the packet portion has been processed, a PPI de-allocation command causes the packet engine to de-allocate the PPI so that the PPI is available for allocating in association with another packet portion.
摘要翻译：在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。不是将PDRSD管理分组部分存储到存储器中，而是提供分组引擎。 PDRSD使用PPI寻址模式与分组引擎进行通信，并指示分组引擎存储分组部分。 PDRSD从分组引擎请求PPI，并由分组引擎分配PPI，然后用PPI标记要写入的分组部分，并将分组部分和PPI发送到分组引擎。一旦分组部分被处理，PPI解除分配命令使分组引擎去分配PPI，使得PPI可用于与另一分组部分相关联地分配。

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