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1. 发明申请

US20060189167A1 Method for fabricating silicon nitride film 审中-公开
标题翻译：氮化硅膜的制造方法
公开(公告)号：US20060189167A1
公开(公告)日：2006-08-24
申请号：US11060907
申请日：2005-02-18
申请人： Hsiang-Ying Wang , Neng-Hui Yang , Huan-Shun Lin
发明人： Hsiang-Ying Wang , Neng-Hui Yang , Huan-Shun Lin
IPC分类号： H01L21/31 , H01L21/44
CPC分类号： H01L29/7843 , C23C16/345 , C23C16/56 , H01L21/02274 , H01L21/3185 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for fabricating a silicon nitride film is disclosed. The method is adapted for a substrate comprising a transistor device. A self-aligned silicide film is formed over the transistor device. A silicon nitride film is then formed over the substrate. A thermal process is performed to the silicon nitride film. The process temperature of the thermal treatment process is lower than 450° C. and the thermal treatment process is performed under an inert gas environment. According to the fabrication method of the present invention, a high tensile stress silicon nitride film can be formed by a process with a low thermal budget. The electron mobility in the channel region of the transistor device can be enhanced without affecting the thermal stability of metal silicide.
摘要翻译：公开了一种制造氮化硅膜的方法。该方法适用于包括晶体管器件的衬底。在晶体管器件上形成自对准的硅化物膜。然后在衬底上形成氮化硅膜。对氮化硅膜进行热处理。热处理工艺的工艺温度低于450℃，热处理工艺在惰性气体环境下进行。根据本发明的制造方法，可以通过具有低热预算的工艺形成高拉伸应力氮化硅膜。可以增强晶体管器件的沟道区域中的电子迁移率，而不影响金属硅化物的热稳定性。

2. 发明授权

US07071046B2 Method of manufacturing a MOS transistor 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US07071046B2
公开(公告)日：2006-07-04
申请号：US10904620
申请日：2004-11-18
申请人： Neng-Hui Yang , Huan-Shun Lin , Hsiang-Ying Wang
发明人： Neng-Hui Yang , Huan-Shun Lin , Hsiang-Ying Wang
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7834 , H01L29/6659 , H01L29/66636
摘要： A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.
摘要翻译：一种制造MOS晶体管的方法，包括以下步骤：提供半导体衬底，在所述半导体衬底上形成栅极结构，执行注入以在所述半导体衬底中分别邻近所述栅极结构形成两个注入区域，执行蚀刻工艺去除每个注入区域并形成沟槽，并进行选择性外延生长以将外延晶体填充到沟槽中，从而形成MOS晶体管的源极/漏极。

3. 发明申请

US20060105511A1 METHOD OF MANUFACTURING A MOS TRANSISTOR 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US20060105511A1
公开(公告)日：2006-05-18
申请号：US10904620
申请日：2004-11-18
申请人： Neng-Hui Yang , Huan-Shun Lin , Hsiang-Ying Wang
发明人： Neng-Hui Yang , Huan-Shun Lin , Hsiang-Ying Wang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7834 , H01L29/6659 , H01L29/66636
摘要： A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.
摘要翻译：一种制造MOS晶体管的方法，包括以下步骤：提供半导体衬底，在所述半导体衬底上形成栅极结构，执行注入以在所述半导体衬底中分别邻近所述栅极结构形成两个注入区域，执行蚀刻工艺去除每个注入区域并形成沟槽，并进行选择性外延生长以将外延晶体填充到沟槽中，从而形成MOS晶体管的源极/漏极。

4. 发明授权

US07060547B2 Method for forming a junction region of a semiconductor device 有权
标题翻译：用于形成半导体器件的接合区域的方法
公开(公告)号：US07060547B2
公开(公告)日：2006-06-13
申请号：US10764437
申请日：2004-01-27
申请人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
发明人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/2256 , H01L21/28176 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.
摘要翻译：公开了一种用于形成半导体器件的接合区域的方法。该方法的步骤包括提供半导体衬底。栅极结构形成在半导体衬底上。将掺杂剂注入到半导体衬底中以形成结区域。在栅极结构和半导体衬底上形成绝缘体层。对绝缘体层进行含碳等离子体处理。在栅极结构的侧壁上形成间隔物，并且将掺杂剂注入到半导体衬底中以在接合区域旁边形成源极/漏极区域。对半导体基板进行热处理。

5. 发明授权

US07435658B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US07435658B2
公开(公告)日：2008-10-14
申请号：US11147506
申请日：2005-06-07
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

6. 发明授权

US06815770B1 MOS transistor having reduced source/drain extension sheet resistance 有权
标题翻译： MOS晶体管具有减少的源极/漏极延伸片电阻
公开(公告)号：US06815770B1
公开(公告)日：2004-11-09
申请号：US10604741
申请日：2003-08-14
申请人： Chin-Cheng Chien , Hsiang-Ying Wang , Yu-Kun Chen , Neng-Hui Yang
发明人： Chin-Cheng Chien , Hsiang-Ying Wang , Yu-Kun Chen , Neng-Hui Yang
IPC分类号： H01L2978
CPC分类号： H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7833
摘要： The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each sidewall of the gate electrode. A lightly doped source/drain extension is formed under the spacer with a raised epitaxial layer interposed between the spacer and the semiconductor substrate. The epitaxial layer, which is part of the lightly doped source/drain extension, has a lattice constant that is greater than the lattice constant of silicon crystal. The epitaxial layer serves as a solubility enhancement layer that is capable of increasing active boron concentration, thereby reducing sheet resistance of the source/drain extension. A heavily doped source/drain region is formed in the semiconductor substrate next to the edge of the spacer. A raised silicide layer is formed on the heavily doped source/drain region.
摘要翻译：本发明提供了一种新型的MOS晶体管结构。 MOS晶体管包括形成在半导体衬底上的栅电极和形成在栅电极和半导体衬底之间的栅氧化层。在栅电极的每个侧壁上形成间隔物。在间隔物之下形成轻掺杂的源极/漏极延伸部，其中插入在间隔物和半导体衬底之间的凸起的外延层。作为轻掺杂源极/漏极延伸部分的外延层具有大于硅晶体的晶格常数的晶格常数。外延层用作能够增加活性硼浓度，从而降低源极/漏极延伸部的薄层电阻的溶解度增强层。在半导体衬底中，在间隔物的边缘附近形成重掺杂的源/漏区。在重掺杂的源极/漏极区域上形成凸起的硅化物层。

7. 发明申请

US20050272213A1 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：制造金属氧化物半导体晶体管的方法
公开(公告)号：US20050272213A1
公开(公告)日：2005-12-08
申请号：US11147506
申请日：2005-06-07
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂源/漏区。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

8. 发明申请

US20050164461A1 Method for forming a junction region of a semiconductor device 有权
标题翻译：用于形成半导体器件的接合区域的方法
公开(公告)号：US20050164461A1
公开(公告)日：2005-07-28
申请号：US10764437
申请日：2004-01-27
申请人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
发明人： Yu-Kun Chen , Neng-Hui Yang , Chin-Cheng Chien , Hsiang-Ying Wang
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L21/2256 , H01L21/28176 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.
摘要翻译：公开了一种用于形成半导体器件的接合区域的方法。该方法的步骤包括提供半导体衬底。栅极结构形成在半导体衬底上。将掺杂剂注入到半导体衬底中以形成结区域。在栅极结构和半导体衬底上形成绝缘体层。对绝缘体层进行含碳等离子体处理。在栅极结构的侧壁上形成间隔物，并且将掺杂剂注入到半导体衬底中以在接合区域旁边形成源极/漏极区域。对半导体基板进行热处理。

9. 发明授权

US06943085B2 Method of manufacturing metal-oxide-semiconductor transistor 有权
公开(公告)号：US06943085B2
公开(公告)日：2005-09-13
申请号：US10667229
申请日：2003-09-17
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.

10. 发明申请

US20050054173A1 Method of manufacturing metal-oxide-semiconductor transistor 有权
标题翻译：金属氧化物半导体晶体管的制造方法
公开(公告)号：US20050054173A1
公开(公告)日：2005-03-10
申请号：US10667229
申请日：2003-09-17
申请人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
发明人： Yu-Ren Wang , Chin-Cheng Chien , Hsiang-Ying Wang , Neng-Hui Yang
IPC分类号： H01L21/265 , H01L21/336 , H01L21/331
CPC分类号： H01L29/6659 , H01L21/26513 , H01L29/6656 , H01L29/66666
摘要： A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer and then a pre-annealing operation is performed. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.
摘要翻译：提供一种制造MOS晶体管的方法。提供其上具有栅极结构的衬底。在栅极结构的侧壁上形成第一间隔物。进行预非晶化注入以使基板的一部分非晶化。在第一间隔物的每一侧上的衬底中形成掺杂的源极/漏极延伸区域。第二间隔件形成在第一间隔件的侧壁上。在第二间隔物的每一侧上的衬底中形成掺杂的源/漏区，然后进行预退火操作。此后，进行固相外延处理以重新结晶衬底的非晶化部分并激活掺杂的源极/漏极延伸区域和掺杂源极/漏极区域以形成源极/漏极端子。最后，执行后退火操作。

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