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1. 发明公开

US20230288378A1 BUFFER ROD, DEVICE AND SYSTEM 审中-公开
公开(公告)号：US20230288378A1
公开(公告)日：2023-09-14
申请号：US17494478
申请日：2021-10-05
申请人： Navin Sakthivel , Aaron Avagliano , Baskaran Ganesan , Wei Chen
发明人： Navin Sakthivel , Aaron Avagliano , Baskaran Ganesan , Wei Chen
IPC分类号： G01N29/28 , G01N29/02 , G01N33/00 , G10K11/02
CPC分类号： G01N29/28 , G01N29/02 , G01N33/005 , G10K11/02 , G01N29/2437
摘要： A buffer rod for an acoustic measurement device including a ceramic nonmetallic body, a window plate disposed at one longitudinal end of the body, an opposite end of the body configured to interact with a transducer.

2. 发明授权

US08793515B2 Increasing power efficiency of turbo mode operation in a processor 有权
公开(公告)号：US08793515B2
公开(公告)日：2014-07-29
申请号：US13169260
申请日：2011-06-27
申请人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
发明人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, Jr. , Suresh Sugumar
IPC分类号： G06F1/26 , G06F9/46 , G06F1/32 , G06F9/50
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

3. 发明申请

US20140149774A1 INCREASING POWER EFFICIENCY OF TURBO MODE OPERATION IN A PROCESSOR 有权
标题翻译：在加工器中提高涡轮模式运行的功率效率
公开(公告)号：US20140149774A1
公开(公告)日：2014-05-29
申请号：US14171148
申请日：2014-02-03
申请人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, JR. , Suresh Sugumar
发明人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, JR. , Suresh Sugumar
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器具有多个核来执行线程。处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。描述和要求保护其他实施例。

4. 发明申请

US20130042126A1 MEMORY LINK POWER MANAGEMENT 有权
标题翻译：存储器链接电源管理
公开(公告)号：US20130042126A1
公开(公告)日：2013-02-14
申请号：US13206923
申请日：2011-08-10
申请人： Baskaran Ganesan , Suresh Sugumar , Vijayanand Naik , Tessil Thomas
发明人： Baskaran Ganesan , Suresh Sugumar , Vijayanand Naik , Tessil Thomas
IPC分类号： G06F1/32
CPC分类号： G06F1/3225 , G06F1/3237 , G06F1/3275 , Y02D10/128 , Y02D10/14 , Y02D50/20
摘要： Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions.Embodiments of the invention may detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards a memory unit, a processor core executing a processor low-power mode, and a processor socket executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit and various components of the memory subsystem.
摘要翻译：本发明的实施例描述了在存储器子系统空闲状态期间改进链路功率管理的系统和过程。当存储器子系统的各个组件在某些操作条件下进入低功率状态时，本发明的实施例控制存储器连接操作。本发明的实施例类似地描述了在检测到某些操作条件时存储器链路和存储器子系统的各种组件的退出低功率状态。本发明的实施例可以检测计算系统中的操作条件。这些操作条件中的一些可以包括但不限于存储器控制器，其不涉及指向存储器单元的事务，执行处理器低功率模式的处理器核心以及执行空闲模式的处理器插座。响应于检测到所述操作条件，本发明的实施例可以为存储器单元和存储器子系统的各种组件执行低功率空闲状态。

5. 发明申请

US20120311360A1 Reducing Power Consumption Of Uncore Circuitry Of A Processor 有权
标题翻译：降低处理器的不确定电路的功耗
公开(公告)号：US20120311360A1
公开(公告)日：2012-12-06
申请号：US13118757
申请日：2011-05-31
申请人： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
发明人： Srikanth Balasubramanian , Tessil Thomas , Satish Shrimali , Baskaran Ganesan
IPC分类号： G06F1/32 , G06F9/02 , G06F15/80
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3237 , G06F1/324 , Y02D10/128 , Y02D50/20
摘要： In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.
摘要翻译：在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。

6. 发明授权

US08954790B2 Fault tolerance of multi-processor system with distributed cache 有权
标题翻译：具有分布式缓存的多处理器系统的容错能力
公开(公告)号：US08954790B2
公开(公告)日：2015-02-10
申请号：US12984500
申请日：2011-01-04
申请人： Thanunathan Rangarajan , Baskaran Ganesan , Binata Bhattacharayya
发明人： Thanunathan Rangarajan , Baskaran Ganesan , Binata Bhattacharayya
IPC分类号： G06F11/00 , G06F11/16 , G06F12/08 , G06F11/20
CPC分类号： G06F11/1666 , G06F11/1658 , G06F11/20 , G06F12/0813 , G06F12/0846 , G06F12/0864
摘要： A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.
摘要翻译：描述了具有用于分布式高速缓存的各个缓存片段的高速缓存代理逻辑电路的不同实例的半导体芯片。半导体芯片还包括散列引擎逻辑电路，包括：散列逻辑电路，用于基于地址确定特定的一个高速缓存片段将接收具有该地址的请求，以及第一输入以接收故障通知特定缓存片段的事件。半导体芯片还包括响应于通知将地址分配给高速缓存片的另一高速缓存片的第一电路。

7. 发明申请

US20130007475A1 EFFICIENT FREQUENCY BOOST OPERATION 有权
标题翻译：有效的频率提升操作
公开(公告)号：US20130007475A1
公开(公告)日：2013-01-03
申请号：US13174958
申请日：2011-07-01
申请人： Baskaran Ganesan , James S. Burns , Suresh Sugumar , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , Dheemanth Nagaraj , Russell J. Fenger
发明人： Baskaran Ganesan , James S. Burns , Suresh Sugumar , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , Dheemanth Nagaraj , Russell J. Fenger
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/08 , Y02D10/126
摘要： Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.
摘要翻译：操作计算系统的系统和方法可以涉及识别多个状态值，其中每个状态值对应于与处理器相关联的计算线程。可以针对多个状态值确定平均值，其中可以至少部分地基于平均值来确定是否授予频率提升请求。

8. 发明申请

US20120331310A1 Increasing Power Efficiency Of Turbo Mode Operation In A Processor 有权
标题翻译：在处理器中提高Turbo模式操作的功率效率
公开(公告)号：US20120331310A1
公开(公告)日：2012-12-27
申请号：US13169260
申请日：2011-06-27
申请人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, JR. , Suresh Sugumar
发明人： James S. Burns , Baskaran Ganesan , Russell J. Fenger , Devadatta V. Bodas , Sundaravarathan R. Iyengar , Feranak Nelson , John M. Powell, JR. , Suresh Sugumar
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/329 , G06F9/5094 , Y02D10/22 , Y02D10/24
摘要： In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器具有多个核来执行线程。处理器还包括功率控制逻辑，用于基于存储核心功率计数的计数器的阈值和识别至少一个线程的turbo模式请求的性能组合之间的比较来进入turbo模式。以这种方式，可以在提供高功率效率的处理器的利用水平上输入turbo模式。描述和要求保护其他实施例。

9. 发明申请

US20120005524A1 FAULT TOLERANCE OF MULTI-PROCESSOR SYSTEM WITH DISTRIBUTED CACHE 有权
标题翻译：具有分布式高速缓存的多处理器系统的容错性
公开(公告)号：US20120005524A1
公开(公告)日：2012-01-05
申请号：US12984500
申请日：2011-01-04
申请人： Thanunathan Rangarajan , Baskaran Ganesan , Binata Bhattacharayya
发明人： Thanunathan Rangarajan , Baskaran Ganesan , Binata Bhattacharayya
IPC分类号： G06F11/20
CPC分类号： G06F11/1666 , G06F11/1658 , G06F11/20 , G06F12/0813 , G06F12/0846 , G06F12/0864
摘要： A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.
摘要翻译：描述了具有用于分布式高速缓存的各个缓存片段的高速缓存代理逻辑电路的不同实例的半导体芯片。半导体芯片还包括散列引擎逻辑电路，包括：散列逻辑电路，用于基于地址确定特定的一个高速缓存片段将接收具有该地址的请求，以及第一输入以接收故障通知特定缓存片段的事件。半导体芯片还包括响应于通知将地址分配给高速缓存片的另一高速缓存片的第一电路。

10. 发明授权

US07533300B2 Configurable error handling apparatus and methods to operate the same 有权
标题翻译：可配置的错误处理设备和操作方法
公开(公告)号：US07533300B2
公开(公告)日：2009-05-12
申请号：US11352961
申请日：2006-02-13
申请人： Suresh Marisetty , Baskaran Ganesan , Gautam Bhagwandas Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose A. Vargas , Jim Crossland , Stan J. Domen
发明人： Suresh Marisetty , Baskaran Ganesan , Gautam Bhagwandas Doshi , Murugasamy Nachimuthu , Koichi Yamada , Jose A. Vargas , Jim Crossland , Stan J. Domen
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0781
摘要： Configurable error handling apparatus and methods to operate the same are disclosed. An example apparatus comprises a processor core in a semiconductor package, a hardware functional block in the semiconductor package, an error handler in the semiconductor package, wherein the error handler is configurable to route error data from the hardware functional block to at least one of a first error log or a second error log and to route error signals from the hardware functional block to at least one of an operating system or firmware, and wherein the processor core configures the error handler and the hardware functional block.
摘要翻译：公开了可配置的错误处理装置及其操作方法。示例性设备包括半导体封装中的处理器核心，半导体封装中的硬件功能块，半导体封装中的错误处理器，其中错误处理程序可配置为将错误数据从硬件功能块路由到至少一个第一错误日志或第二错误日志，并将来自硬件功能块的错误信号路由到操作系统或固件中的至少一个，并且其中处理器核心配置错误处理程序和硬件功能块。

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