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1. 发明授权

US6112307A Method and apparatus for translating signals between clock domains of different frequencies 失效
标题翻译：用于在不同频率的时钟域之间翻译信号的方法和装置
公开(公告)号：US6112307A
公开(公告)日：2000-08-29
申请号：US552460
申请日：1995-11-09
申请人： Jasmin Ajanovic , Dahmane Dahmani , Kenneth Chris Holland , Narendra Khandekar
发明人： Jasmin Ajanovic , Dahmane Dahmani , Kenneth Chris Holland , Narendra Khandekar
IPC分类号： G06F1/12 , H04L7/00 , H04L7/02 , G06F1/08
CPC分类号： G06F1/12 , H04L7/0012 , H04L7/02
摘要： A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.
摘要翻译：同步电路将慢时钟域中的信号转换为快速时钟域。慢时钟频率是快时钟频率的一个倍数。在慢时钟的频率下产生同步脉冲信号，但是与快速时钟相位同步。采用同步脉冲信号对慢时钟域中的信号进行门控，使其在快速时钟域中同步。在快速时钟频率和慢时钟频率之间的比率由频率除数信号确定的系统中，采用窥探电路来捕获频率除数信号以实现时钟域之间的快速同步。

2. 发明授权

US5519872A Fast address latch with automatic address incrementing 失效
标题翻译：快速地址锁存器，自动地址递增
公开(公告)号：US5519872A
公开(公告)日：1996-05-21
申请号：US175589
申请日：1993-12-30
申请人： Narendra Khandekar , Dahmane Dahmani , Jasmin Ajanovic
发明人： Narendra Khandekar , Dahmane Dahmani , Jasmin Ajanovic
IPC分类号： G06F13/42 , G06F13/364
CPC分类号： G06F13/4217
摘要： A latching mechanism captures an address transmitted on a multiplexed address/data bus and preserves it for the full bus cycle. A transparent latch with a multiplexed feedback path allows the address to be quickly captured and decoded. An additional multiplexer and latch cooperate with the first mentioned latch to keep the address stable for a sufficient time to allow latching by slower memory elements. Additional elements are provided to automatically increment the address for multiple data burst operation.
摘要翻译：锁存机制捕获在复用的地址/数据总线上发送的地址，并将其保留在整个总线周期。具有复用反馈路径的透明锁存器允许快速捕获和解码地址。一个附加的多路复用器和锁存器与第一个提到的锁存器配合，以保持地址稳定足够的时间以允许较慢存储器元件的锁存。提供附加元件以自动递增多个数据突发操作的地址。

3. 发明授权

US6026455A Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system 失效
标题翻译：用于为重试总线主机向计算机系统中连接两条总线的数据传输桥提供有保障的访问的架构和方法
公开(公告)号：US6026455A
公开(公告)日：2000-02-15
申请号：US201817
申请日：1994-02-24
申请人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
发明人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
IPC分类号： G06F13/40 , G06F13/36
CPC分类号： G06F13/4031
摘要： A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
摘要翻译：适于与PCI和辅助总线电路相关联的桥接电路，桥接电路包括用于存储特定PCI总线主机尝试访问辅助总线并已被迫重试该接入的指示的电路，用于屏蔽的电路任何重试直到总线再次可用，以及用于提供间隔时间的电路，在该间隔期间，重试PCI总线主机被保证访问辅助总线，有利于在总线被放弃之后辅助总线上的总线主机，使得重试次序不会产生导致PCI总线带宽损失的操作。

4. 发明授权

US5664117A Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer 失效
标题翻译：用于预取数据以在计算机中的两条总线之间的桥中加载缓冲器的装置和方法
公开(公告)号：US5664117A
公开(公告)日：1997-09-02
申请号：US603688
申请日：1996-01-20
申请人： Nilesh Shah , Jasmin Ajanovic , Dahmane Dahmani
发明人： Nilesh Shah , Jasmin Ajanovic , Dahmane Dahmani
IPC分类号： G06F5/06 , G06F13/40 , G06F13/00
CPC分类号： G06F5/065 , G06F13/4059
摘要： A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.
摘要翻译：一种提供在计算机系统中的第一总线和第二总线之间有效数据传输的桥接电路。桥接电路接收指示存储要求从第一总线传送到第二总线的数据段的存储位置的地址。获取电路从第一总线获取所请求的数据，并且在存储所请求的数据的存储器位置之后顺序地预取存储在存储单元中的一个或多个附加数据段。预取的数据段存储在缓冲器中，以便通过后续数据传输请求立即访问。响应于接收到对应于地址输入电路上的特定数据段的地址，供应电路将每个数据段从缓冲器传送到第二总线。

5. 发明授权

US5666556A Method and apparatus for redirecting register access requests wherein the register set is separate from a central processing unit 失效
标题翻译：用于重定向寄存器访问请求的方法和装置，其中寄存器集与中央处理单元分离
公开(公告)号：US5666556A
公开(公告)日：1997-09-09
申请号：US710572
申请日：1996-09-19
申请人： Narendra Khandekar , Jasmin Ajanovic
发明人： Narendra Khandekar , Jasmin Ajanovic
IPC分类号： G06F13/40 , G06F12/06
CPC分类号： G06F13/4027
摘要： A register address space is defined with a capacity large enough to accommodate substantial growth in the number of required registers. Unused register locations are reserved for future use. Access requests directed to reserved addresses are redirected to a physical register containing the same stored value that would be returned if a physical register were associated with the reserved address to which the access was originally directed. The physical register is separate from any central processing unit.
摘要翻译：寄存器地址空间被定义为具有足够大的容量以容纳所需寄存器的数量的显着增长。未使用的寄存器位置保留供将来使用。指向保留地址的访问请求被重定向到物理寄存器，该物理寄存器包含与物理寄存器与访问最初指向的保留地址相关联时返回的相同存储值。物理寄存器与任何中央处理单元分开。

6. 发明授权

US09741384B1 Non-rotating optical storage 有权
公开(公告)号：US09741384B1
公开(公告)日：2017-08-22
申请号：US15357774
申请日：2016-11-21
申请人： Jasmin Ajanovic
发明人： Jasmin Ajanovic
IPC分类号： G11B7/00 , G11B7/09 , G11B7/005 , G11B7/013 , G11B7/127 , G11B7/1362
CPC分类号： G11B7/09 , G11B7/005 , G11B7/007 , G11B7/013 , G11B7/085 , G11B7/127 , G11B7/1362
摘要： Systems and methods for long-term non-volatile non-rotating optical storage of digital information rely on storage elements that include optical storage media, an access subsystem configured to access bits of information from one of the storage elements, and a support structure configured to support multiple storage elements. A laser used to retrieve and/or record bits of digital information may be moved along two orthogonal dimensions while the storage element is non-rotating.

7. 发明申请

US20140307748A1 Packetized Interface For Coupling Agents 审中-公开
标题翻译：耦合代理的分组接口
公开(公告)号：US20140307748A1
公开(公告)日：2014-10-16
申请号：US14310164
申请日：2014-06-20
申请人： Mahesh Wagh , Abhishek Singhal , Jasmin Ajanovic
发明人： Mahesh Wagh , Abhishek Singhal , Jasmin Ajanovic
IPC分类号： H04L29/06
CPC分类号： H04L69/22 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an on-chip protocol and a packetization layer coupled to the fabric to receive command and data information from the fabric on multiple links and to packetize the information into a packet for transmission from the die to another die via an in-package packetized link. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括在第一半导体管芯上的结构，以根据片上协议与管芯上的至少一个代理进行通信，以及耦合到该结构的分组层，以从该结构接收命令和数据信息多个链路并且将信息分组成分组，以经由内部分组化链路从芯片传输到另一个管芯。描述和要求保护其他实施例。

8. 发明申请

US20140185436A1 GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL 审中-公开
标题翻译：一般输入/输出结构，协议和相关方法实施流量控制
公开(公告)号：US20140185436A1
公开(公告)日：2014-07-03
申请号：US14145384
申请日：2013-12-31
申请人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
发明人： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC分类号： H04L12/801
CPC分类号： H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
摘要： A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel.
摘要翻译：提供存储装置以维持为信道上的设备分配的流量控制信用的值，并且提供流控制逻辑以通过互连的链路接收流控制信号，所述流控制信号指示为设备在通道上。流量控制逻辑还基于通道上的设备的活动来更新流量控制信用的值。

9. 发明授权

US08549183B2 PCI express enhancements and extensions 有权
公开(公告)号：US08549183B2
公开(公告)日：2013-10-01
申请号：US12883781
申请日：2010-09-16
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

10. 发明授权

US08473642B2 PCI express enhancements and extensions including device window caching 有权
标题翻译： PCI Express增强功能和扩展功能，包括设备窗口缓存
公开(公告)号：US08473642B2
公开(公告)日：2013-06-25
申请号：US13198559
申请日：2011-08-04
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Abraham Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

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