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1. 发明授权

US6049887A Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio 失效
标题翻译：在以非整数频率比工作的同步时钟域之间传播信号的方法和装置
公开(公告)号：US6049887A
公开(公告)日：2000-04-11
申请号：US985390
申请日：1997-12-04
申请人： Narendra Khandekar , Ashish S. Gadagkar , Robert F. Kubick , Vincent E. VonBokern , Manish Muthal
发明人： Narendra Khandekar , Ashish S. Gadagkar , Robert F. Kubick , Vincent E. VonBokern , Manish Muthal
IPC分类号： G06F1/10 , G06F11/00
CPC分类号： G06F1/10
摘要： A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.
摘要翻译：将信号从第一时钟域发送到第二时钟域的方法从产生第一和第二时钟信号开始。第一和第二时钟信号基本上是同步的并且具有非整数倍的相应频率。响应于基本上与第二时钟信号的转换相关的第一时钟信号的转变而在第一时钟域中产生的第一信号被防止被锁存在第二时钟域中，第二个时钟信号。防止第一时钟信号被锁存大于可能存在于第一和第二时钟信号之间的最大时钟偏移的时间段。

2. 发明授权

US5961649A Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio 失效
标题翻译：在以非整数频率比工作的同步时钟域之间传播信号的方法和装置
公开(公告)号：US5961649A
公开(公告)日：1999-10-05
申请号：US985391
申请日：1997-12-04
申请人： Narendra Khandekar , Ashish S. Gadagkar , Robert F. Kubick , Vincent E. VonBokern , Manish Muthal
发明人： Narendra Khandekar , Ashish S. Gadagkar , Robert F. Kubick , Vincent E. VonBokern , Manish Muthal
IPC分类号： G06F5/06 , G06F1/72
CPC分类号： G06F5/06
摘要： A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.
摘要翻译：描述了将信号从相对较快的时钟域发送到相对慢的时钟域的方法。快速和慢速时钟域根据基本同步的相应的快速和慢速时钟信号进行操作，并且具有非整数倍的相应频率。输入信号的第一状态在快时钟信号的第一周期的开始时被锁存，快速时钟信号的第一周期的开始基本上与慢时钟信号的第一周期的开始一致。响应于输入信号的第一状态的锁存，在快速时钟信号的第一周期和至少另外一个周期内产生并保持第一输出信号。响应于慢时钟信号的第二周期的开始，第一输出信号在第二时域被锁存，第二周期紧接在慢时钟信号的第一周期之后。

3. 发明授权

US5815167A Method and apparatus for providing concurrent access by a plurality of agents to a shared memory 失效
标题翻译：用于提供由多个代理程序并发访问共享存储器的方法和装置
公开(公告)号：US5815167A
公开(公告)日：1998-09-29
申请号：US672099
申请日：1996-06-27
申请人： Manish Muthal , Nilesh V. Shah , Kuljit Bains
发明人： Manish Muthal , Nilesh V. Shah , Kuljit Bains
IPC分类号： G06T1/60 , G06F12/06 , G06F13/16 , G06F13/18 , G06F15/16 , G06F15/167 , G06T1/20 , G09G5/00
CPC分类号： G06F15/167 , G06F13/1647
摘要： A computer system, including a graphics controller and a memory controller, employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form a bank of DRAMs. The shared memory is accessible by both the memory and graphics controllers. The memory includes a shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined. An interface selectively provides access to the shared DRAM row by the graphics or memory controller, while providing permanent access to the remaining DRAM rows by the memory controller. This facilitates concurrent access by the graphics controller and the memory controller to the shared DRAM row and to the remaining DRAM rows respectively, in a first memory access scenario. The accessibility of the shared DRAM row by the memory controller, in a second memory access scenario, is also maintained. The interface includes a selector circuit, such as a multiplexor or Q-switch, coupled to receive memory address signals and control signals from the graphics controller and the memory controller via a dedicated bus from each of these controllers. The selector circuit is operable selectively to present either memory address to the shared DRAM row, in which the SFB aperture is defined, and also selectively to provide access to the shared DRAM row by either controller. The selector circuit is operable by a logic circuit, incorporated within the systems controller, which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row, or in the remaining DRAM rows.
摘要翻译：包括图形控制器和存储器控制器的计算机系统采用共享帧缓冲器架构，因此具有一组DRAM形式的共享存储器。共享内存可由内存和图形控制器访问。存储器包括共享DRAM行，其中定义了共享帧缓冲器（SFB）孔径。接口选择性地提供对图形或存储器控制器对共享DRAM行的访问，同时由存储器控制器永久地访问剩余的DRAM行。这有助于在第一存储器访问场景中分别由图形控制器和存储器控制器同时访问共享的DRAM行和剩余的DRAM行。在第二存储器访问场景中，存储器控制器的共享DRAM行的可访问性也被保持。该接口包括诸如多路复用器或Q开关的选择器电路，其经由来自这些控制器中的每一个的专用总线耦合以从图形控制器和存储器控制器接收存储器地址信号和控制信号。选择器电路可选择地可操作地将存储器地址呈现给共享DRAM行，其中定义了SFB孔径，并且还选择性地通过任一控制器提供对共享DRAM行的访问。选择器电路可由逻辑电路操作，该逻辑电路包括在系统控制器内，该逻辑电路确定从存储器控制器接收到的存储器访问请求是否是共享DRAM行中的地址或剩余的DRAM行中的地址。

4. 发明授权

US07292586B2 Micro-programmable protocol packet parser and encapsulator 失效
标题翻译：微型可编程协议包解析器和封装器
公开(公告)号：US07292586B2
公开(公告)日：2007-11-06
申请号：US09823802
申请日：2001-03-30
申请人： Gautam Dewan , Prabhas Kejriwal , Manish Muthal , Shashank Merchant , Chi Fai Ho
发明人： Gautam Dewan , Prabhas Kejriwal , Manish Muthal , Shashank Merchant , Chi Fai Ho
IPC分类号： H04L12/28
CPC分类号： H04L29/06 , G06F9/3885 , H04L69/12 , H04L69/22
摘要： A micro-programmable controller is disclosed for parsing a packet and encapsulating data to form a packet. The micro-programmable controller loads an instruction within the micro-controller. The instruction word has a plurality of instruction fields. The micro-controller processes the plurality of instruction fields in parallel. Each instruction field is related to a specific operation for parsing a packet or encapsulating data to form a packet. The programmable micro-controller can be programmed to handle packets to support new types of protocols by programming a template to string specific routines together based on an instruction set specific for parsing and encapsulating.
摘要翻译：公开了一种用于解析分组并封装数据以形成分组的微型可编程控制器。微型可编程控制器加载微控制器内的指令。指令字具有多个指令字段。微控制器并行处理多个指令字段。每个指令字段与用于解析分组或封装数据以形成分组的特定操作有关。可编程微控制器可以编程为处理数据包以支持新类型的协议，方法是根据特定于解析和封装的指令集将模板编程到一起，将特定于特定的例程进行编程。

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