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1. 发明授权

US06959365B2 Microcomputer including a flash memory and a flash memory rewrite program stored therein 有权
标题翻译：微型计算机包括闪存和存储在其中的闪存重写程序
公开(公告)号：US06959365B2
公开(公告)日：2005-10-25
申请号：US10138567
申请日：2002-05-06
申请人： Naoki Ootani , Yoshio Kasai , Toshihiro Abe , Mitsuru Sugita
发明人： Naoki Ootani , Yoshio Kasai , Toshihiro Abe , Mitsuru Sugita
IPC分类号： G06F12/00 , G06F12/02 , G06F15/78
CPC分类号： G06F12/0246
摘要： A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).
摘要翻译：获得具有内置闪存的微型计算机，其中闪存可以被保存在闪速存储器上的重写程序适当地重写，而不需要额外的复杂控制电路。在接受构成重写命令的擦除/写入命令时，闪速存储器模块（2）在执行一系列处理期间向闪速存储器控制电路（3）输出表示忙状态的就绪状态信号RYIBY。当就绪状态信号RYIBY表示忙碌状态时，闪速存储器控制电路（3）将保持信号HOLD输出为“H”，以阻止CPU（1）访问闪存模块（2）。当就绪状态信号RYIBY恢复就绪状态时，闪速存储器控制电路（3）将保持信号HOLD输出为“L”，以允许CPU（1）访问闪存模块（2）。

2. 发明授权

US06757195B2 Flash memory having enhanced yield and having enhanced reliability in redundant and dummy circuits 失效
标题翻译：闪存具有增强的产量并且在冗余和虚拟电路中具有增强的可靠性
公开(公告)号：US06757195B2
公开(公告)日：2004-06-29
申请号：US10193252
申请日：2002-07-12
申请人： Toshihiro Abe , Yoshio Kasai , Naoki Ootani , Mitsuru Sugita
发明人： Toshihiro Abe , Yoshio Kasai , Naoki Ootani , Mitsuru Sugita
IPC分类号： G11C1606
CPC分类号： G11C29/808 , G11C29/832 , G11C29/838
摘要： Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.
摘要翻译：冗余电路11至15分别对应于存储块1至5提供。位线BL0至BL15位于存储块的两侧。备用位线SBL1和SBL2位于冗余电路11至15的两侧。当除了预定的存储器块（例如，引导块）2之外的存储器块5中存在存储单元故障时，当对应于存储单元故障被替换为备用位线SBL1，开关56和76中的每一个对应于备用位线SBL1而处于导通状态。此外，开关48和88中的每一个对应于位线BL8而处于导通状态。结果，备用位线SBL1使与存储块2相对应的冗余电路12转换为与存储器块2连接。

3. 发明授权

US5714406A Method for forming film on semiconductor substrate by thermal CVD method 失效
标题翻译：通过热CVD法在半导体衬底上形成膜的方法
公开(公告)号：US5714406A
公开(公告)日：1998-02-03
申请号：US640257
申请日：1996-04-30
申请人： Takashi Suzuki , Akihito Yamamoto , Hiroshi Ogino , Yoshio Kasai
发明人： Takashi Suzuki , Akihito Yamamoto , Hiroshi Ogino , Yoshio Kasai
IPC分类号： C23C16/44 , C23C16/46 , H01L21/205 , H01L21/302
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： A semiconductor substrate is supported on a lower electrode provided within a chamber. The semiconductor substrate is heated up to about 600.degree. to 700.degree. by radiation heat from a halogen lamp. While the pressure within the chamber is reduced to about 0.1 to 1 Torr, the lower electrode is used as a positive electrode, and an upper electrode is used as a negative electrode. In this state, a DC voltage of 20 V is applied from a DC power supply. Then, a material gas is introduced into the chamber via an introducing hole, and a polysilicon film is grown on an oxide film on the semiconductor substrate. Electricity in the oxide film increases an initial growth rate of the polysilicon film and prevents formation of pinholes in the polysilicon film.
摘要翻译：半导体基板被支撑在设置在室内的下电极上。通过来自卤素灯的辐射热将半导体衬底加热至约600℃至700℃。虽然室内的压力降低到约0.1至1乇，但是下电极用作正电极，并且上电极用作负电极。在该状态下，从直流电源施加20V的直流电压。然后，通过导入孔将原料气体引入室内，在半导体基板上的氧化膜上生长多晶硅膜。氧化膜中的电流增加了多晶硅膜的初始生长速率并且防止了在多晶硅膜中形成针孔。

4. 发明申请

US20080271989A1 APPARATUS FOR PLATING AND METHOD FOR CONTROLLING PLATING 审中-公开
标题翻译：用于控制镀层的镀层和方法
公开(公告)号：US20080271989A1
公开(公告)日：2008-11-06
申请号：US12108296
申请日：2008-04-23
申请人： Fumito Shoji , Yoshio Kasai , Kazuhiro Murakami
发明人： Fumito Shoji , Yoshio Kasai , Kazuhiro Murakami
IPC分类号： C23C14/00
CPC分类号： C25D21/18 , C25D17/00 , C25D21/12
摘要： An apparatus for plating includes a plating bath for plating copper (Cu) film on the surface of a substrate under a prescribed plating condition using a plating solution, a chemical supplying unit for supplying each components constituting the plating solution into the plating bath, a plating solution analyzing unit for analyzing a concentration of a predetermined component contained in the plating solution, a plating controlling unit for storing correlation data between a parameter representing a state of the plating solution and the plating condition, extracting the parameter relating the plating solution, and determining the predetermined plating condition based on the parameter and the stored correlation data.
摘要翻译：一种电镀装置，其特征在于，使用电镀液，在规定的电镀条件下，在基板表面上镀铜（Cu）膜的电镀液，将构成电镀液的各成分供给电镀槽的化学供给单元，溶液分析单元，用于分析包含在电镀溶液中的预定组分的浓度;电镀控制单元，用于存储表示电镀液的状态的参数与电镀条件之间的相关数据，提取与电镀液相关的参数，以及确定基于参数和存储的相关数据的预定电镀条件。

5. 发明授权

US06171977B2 Semiconductor device applied to composite insulative film manufacturing method thereof 失效
标题翻译：半导体装置应用于复合绝缘膜的制造方法
公开(公告)号：US06171977B2
公开(公告)日：2001-01-09
申请号：US08777098
申请日：1996-12-30
申请人： Yoshio Kasai , Takashi Suzuki , Takanori Tsuda , Yuuichi Mikata , Hiroshi Akahori , Akihito Yamamoto
发明人： Yoshio Kasai , Takashi Suzuki , Takanori Tsuda , Yuuichi Mikata , Hiroshi Akahori , Akihito Yamamoto
IPC分类号： H01L2131
CPC分类号： H01L29/66181 , H01L21/28167 , H01L21/3185
摘要： A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800° C. to 1200° C. and the partial pressures of H2O and O2 are set at 1×10−4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained. Then, an electrode for the composite insulative film is formed in the trench.
摘要翻译：清洁在沟槽的内表面形成有杂质扩散层的半导体晶片。将半导体晶片插入炉中，并将NH 3气体在低压条件下引入炉中以产生温度设定在800℃至1200℃的气氛，并且将H 2 O和 O2设定在1×10-4乇或更低。去除形成在沟槽内表面上的自然氧化膜，并且基本上同时在杂质扩散层上形成氮化氮膜。然后，在氮化硅膜上形成CVD氮化硅膜，而不会在同一炉内将氮化氮膜暴露于外部空气。接着，在CVD氮化膜上形成氧化硅膜。结果，得到由氮化物膜，CVD氮化硅膜和氧化硅膜形成的复合绝缘膜。然后，在沟槽中形成用于复合绝缘膜的电极。

6. 发明申请

US20050196914A1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050196914A1
公开(公告)日：2005-09-08
申请号：US11061531
申请日：2005-02-22
申请人： Yoshio Kasai , Miki Kawase , Takashi Suzuki , Motoya Kishida
发明人： Yoshio Kasai , Miki Kawase , Takashi Suzuki , Motoya Kishida
IPC分类号： H01L27/108 , H01L21/8234 , H01L21/8242
CPC分类号： H01L27/10829 , H01L27/10867
摘要： A method of manufacturing a semiconductor device, which comprises forming a first semiconductor film on a surface of a semiconductor substrate, adsorbing a first impurity on a surface of the first semiconductor film, adsorbing a second impurity on the surface of the first semiconductor film, forming a second semiconductor film on the surface of the first semiconductor film, and solid-phase-diffusing the first impurity and the second impurity into a region of the semiconductor substrate which is located adjacent to the first and second semiconductor films to thereby form a first diffusion region containing the first impurity and a second diffusion region containing the second impurity, a concentration of the first impurity in the first diffusion region being higher than that of the second impurity in the second diffusion region, and the first diffusion region having the bottom thereof covered by the second diffusion region.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底的表面上形成第一半导体膜，在第一半导体膜的表面上吸附第一杂质，在第一半导体膜的表面上吸附第二杂质，形成在所述第一半导体膜的表面上的第二半导体膜，并且将所述第一杂质和所述第二杂质固相扩散到所述半导体衬底的与所述第一和第二半导体膜相邻的区域中，从而形成第一扩散含有第一杂质的区域和含有第二杂质的第二扩散区域，第一扩散区域中的第一杂质的浓度高于第二扩散区域中的第二杂质浓度，第一扩散区域的底部被覆盖通过第二扩散区域。

7. 发明授权

US5313600A System for controlling the number of data pieces in a queue memory 失效
标题翻译：用于控制队列存储器中数据段数的系统
公开(公告)号：US5313600A
公开(公告)日：1994-05-17
申请号：US928144
申请日：1992-08-11
申请人： Yoshio Kasai
发明人： Yoshio Kasai
IPC分类号： G06F5/06 , G06F9/30 , G06F9/38 , G06F9/22
CPC分类号： G06F9/3814 , G06F5/06 , G06F9/30149 , G06F9/30152 , G06F9/322 , G06F9/3802
摘要： A system for controlling the number of data pieces in a queue memory includes a counter comprising a plurality of counting circuits each of which adds the current effective data piece number of the instruction queue to an associated, preselected value derived from the difference between a detectable input data piece number and a particular output data piece number. A selector responsive to a selecting signal provided by a queue controller selects one of the counting circuits with the associated preselected value equal to the difference between the current input data piece number and the current output data piece number to provide the effective data piece number. The queue controller calculates this difference and provides it as the selecting signal to the selector.
摘要翻译：一种用于控制队列存储器中的数据片段数量的系统，包括一个计数器，它包括多个计数电路，每个计数电路将指令队列的当前有效数据段号添加到从可检测输入数据段号和特定输出数据段号。响应于由队列控制器提供的选择信号的选择器选择一个计数电路，其中相关联的预选值等于当前输入数据段号与当前输出数据段号之间的差值，以提供有效数据段号。队列控制器计算该差异并将其提供给选择器的选择信号。

8. 发明授权

US5220672A Low power consuming digital circuit device 失效
标题翻译：低功耗数字电路器件
公开(公告)号：US5220672A
公开(公告)日：1993-06-15
申请号：US813238
申请日：1991-12-23
申请人： Yuichi Nakao , Yoshio Kasai
发明人： Yuichi Nakao , Yoshio Kasai
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , Y02B60/1217
摘要： A method is provided for decreasing the power consumption of a sequential digital circuit having a plurality of states being determined from the current state and the input conditions and entered upon the assertion of a pulse from one or more clocks. The method consists of interrupting the switching created by the clock pulses and maintaining the system in a quiescent state. It is first determined whether a subsequent clock pulse will lead to a change in the state of the circuit. If it will, the circuit either waits for a change in the input conditions and state of the circuit, or changes some of the input conditions, depending on the embodiment of the invention. When a circuit configuration is reached in which further clock pulses will not lead to a change in the state of the circuit, the clock signal(s) are replaced by continuously asserted signals. The feedback loop thus created maintains the current state of the circuit in the absence of a clock signal and prevents further switching in the circuit.
摘要翻译：提供了一种降低从当前状态和输入条件确定的多个状态的顺序数字电路的功耗的方法，并且在从一个或多个时钟脉冲的断言中输入。该方法包括中断由时钟脉冲产生的切换并保持系统处于静止状态。首先确定后续时钟脉冲是否会导致电路状态的改变。如果这样，根据本发明的实施例，电路或者等待输入条件和电路状态的改变，或改变一些输入条件。当达到其中进一步的时钟脉冲不会导致电路状态改变的电路配置时，时钟信号由连续断言的信号代替。由此产生的反馈环路在没有时钟信号的情况下保持电路的当前状态，并防止电路中的进一步开关。

9. 发明申请

US20110031576A1 SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：固态成像装置及其制造方法
公开(公告)号：US20110031576A1
公开(公告)日：2011-02-10
申请号：US12722716
申请日：2010-03-12
申请人： Seiichi Iwasa , Yoshio Kasai , Takeshi Yousyou , Tsutomu Sato , Atsushi Murakoshi
发明人： Seiichi Iwasa , Yoshio Kasai , Takeshi Yousyou , Tsutomu Sato , Atsushi Murakoshi
IPC分类号： H01L27/146 , H01L21/265
CPC分类号： H01L21/26513 , H01L21/2652 , H01L27/1463 , H01L27/14689
摘要： A solid-state imaging device includes a first-conductive semiconductor layer, a second-conductive semiconductor layer that is provided on the first-conductive semiconductor layer, a light receiving element that is formed in the second-conductive semiconductor layer, and an element isolation region that is formed to surround the light receiving element in an in-plane direction of the second-conductive semiconductor layer, in which the element isolation region includes a first-conductive first element isolation unit that is connected to the first-conductive semiconductor layer, a hollow that is formed on the first-conductive first element isolation unit, and a first-conductive second element isolation unit that is formed on the hollow.
摘要翻译：固态成像装置包括：第一导电半导体层，设置在第一导电半导体层上的第二导电半导体层，形成在第二导电半导体层中的光接收元件，以及元件隔离区域，其形成为在第二导电半导体层的面内方向上包围光接收元件，其中元件隔离区域包括连接到第一导电半导体层的第一导电第一元件隔离单元，形成在所述第一导电性第一元件隔离单元上的中空部，以及形成在所述中空部上的第一导电性第二元件隔离单元。

10. 发明授权

US4664615A Method and device for shaping or molding stick cosmetics 失效
标题翻译：用于成型或成型棒状化妆品的方法和装置
公开(公告)号：US4664615A
公开(公告)日：1987-05-12
申请号：US804764
申请日：1985-12-05
申请人： Seiya Ohtomo , Minoru Aoki , Yoshio Kasai
发明人： Seiya Ohtomo , Minoru Aoki , Yoshio Kasai
IPC分类号： A45D40/16 , B29C39/02 , B29C39/28
CPC分类号： A45D40/16 , B29C39/02 , B29L2031/718 , Y10S425/803
摘要： Apparatus for molding stick cosmetics, which comprises:closely fitting a molding block into a vertically extending annular member formed around a container charged with a liquid feed composition for solid cosmetics, said molding block having therethrough a plurality of longitudinal slots which are open at both ends;filling said liquid feed composition into said longitudinal slots; and, thereafter,solidifying and drying the thus filled liquid feed composition.
摘要翻译：用于成型棒状化妆品的装置，其包括：将模制块紧密地装配到围绕装有用于固体化妆品的液体进料组合物的容器上形成的垂直延伸的环形构件中，所述模制块具有穿过其中两端敞开的多个纵向狭槽 ; 将所述液体进料组合物填充到所述纵向槽中; 然后固化并干燥如此填充的液体进料组合物。

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