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1. 发明申请

US20120231361A1 FUEL CELL 有权
标题翻译：燃料电池
公开(公告)号：US20120231361A1
公开(公告)日：2012-09-13
申请号：US13423893
申请日：2012-03-19
申请人： Naoki IWAMURA , Hirofumi KAN , Daisuke WATANABE , Hidenori SUZUKI , Shunsuke KIMURA
发明人： Naoki IWAMURA , Hirofumi KAN , Daisuke WATANABE , Hidenori SUZUKI , Shunsuke KIMURA
IPC分类号： H01M8/04
CPC分类号： H01M8/04544 , H01M8/04201 , H01M8/04388 , H01M8/04559 , H01M8/04626 , H01M8/04753 , H01M8/1011 , Y02E60/50 , Y02E60/523
摘要： A fuel cell has a fuel cell main body, a fuel supply unit, a voltage sensor, a supply speed determining unit, a fuel supply control unit, and a connecting unit. The voltage sensor measures the open-circuit voltage of the fuel cell main body. The supply speed determining unit determines the fuel supply speed of the fuel supply unit, on the basis of the results obtained from the measurement performed by the voltage sensor, in the case where the voltage measured by the voltage sensor is smaller than a predetermined value. The fuel supply control unit controls, on the basis of the supply speed thus determined, the fuel supply from the fuel supply unit. The connecting unit connects a load to the fuel cell main body, in the case where the voltage measured by the voltage sensor is larger than the predetermined value.
摘要翻译：燃料电池具有燃料电池主体，燃料供给单元，电压传感器，供给速度确定单元，燃料供给控制单元和连接单元。电压传感器测量燃料电池主体的开路电压。在由电压传感器测量的电压小于预定值的情况下，供电速度确定单元基于由电压传感器执行的测量获得的结果来确定燃料供应单元的燃料供应速度。燃料供给控制单元基于如此确定的供给速度来控制来自燃料供给单元的燃料供给。在由电压传感器测量的电压大于预定值的情况下，连接单元将负载连接到燃料电池主体。

2. 发明申请

US20150255708A1 ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电子设备及其制造方法
公开(公告)号：US20150255708A1
公开(公告)日：2015-09-10
申请号：US14559546
申请日：2014-12-03
申请人： Cha-Deok DONG , Daisuke WATANABE , Kazuya SAWADA , Young-Min EEH , Koji UEDA , Toshihiko NAGASE
发明人： Cha-Deok DONG , Daisuke WATANABE , Kazuya SAWADA , Young-Min EEH , Koji UEDA , Toshihiko NAGASE
IPC分类号： H01L43/02 , H01L43/12 , H01L27/22 , G06F12/08
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/12
摘要： An electronic device that includes a first structure including a first magnetic layer, a second magnetic layer, and a tunnel barrier layer which is interposed between the first magnetic layer and the second magnetic layer; and a second structure disposed over the first structure, and including a magnetic correction layer for correcting a magnetic field of the first structure, wherein a width of a bottom surface of the second structure is larger than a width of a top surface of the first structure.
摘要翻译：一种电子设备，其包括：第一结构，其包括介于所述第一磁性层和所述第二磁性层之间的第一磁性层，第二磁性层和隧道势垒层; 以及设置在所述第一结构上的第二结构，并且包括用于校正所述第一结构的磁场的磁性校正层，其中所述第二结构的底表面的宽度大于所述第一结构的顶表面的宽度。

3. 发明申请

US20140286084A1 MAGNETORESISTIVE ELEMENT 有权
标题翻译：磁电元件
公开(公告)号：US20140286084A1
公开(公告)日：2014-09-25
申请号：US13963654
申请日：2013-08-09
申请人： Daisuke WATANABE , Youngmin EEH , Kazuya SAWADA , Koji UEDA , Toshihiko NAGASE
发明人： Daisuke WATANABE , Youngmin EEH , Kazuya SAWADA , Koji UEDA , Toshihiko NAGASE
IPC分类号： G11C11/16 , H01L43/02
CPC分类号： H01L43/10 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
摘要： According to one embodiment, a magnetoresistive element comprises a storage layer having perpendicular magnetic anisotropy with respect to a film plane and having a variable direction of magnetization, a reference layer having perpendicular magnetic anisotropy with respect to the film plane and having an invariable direction of magnetization, a tunnel barrier layer formed between the storage layer and the reference layer and containing O, and an underlayer formed on a side of the storage layer opposite to the tunnel barrier layer. The reference layer comprises a first reference layer formed on the tunnel barrier layer side and a second reference layer formed opposite the tunnel barrier layer. The second reference layer has a higher standard electrode potential than the underlayer.
摘要翻译：根据一个实施例，磁阻元件包括相对于膜平面具有垂直磁各向异性且具有可变磁化方向的存储层，具有相对于膜平面具有垂直磁各向异性且具有不变的磁化方向的参考层形成在存储层和参考层之间并且包含O的隧道势垒层，以及形成在与隧道势垒层相对的存储层侧的底层。参考层包括形成在隧道势垒层侧的第一参考层和与隧道势垒层相对形成的第二参考层。第二参考层具有比底层更高的标准电极电位。

4. 发明申请

US20120101372A1 DIAGNOSIS SUPPORT APPARATUS, DIAGNOSIS SUPPORT METHOD, LESIONED PART DETECTION APPARATUS, AND LESIONED PART DETECTION METHOD 审中-公开
标题翻译：诊断支持装置，诊断支持方法，部件检测装置和部件检测方法
公开(公告)号：US20120101372A1
公开(公告)日：2012-04-26
申请号：US13280259
申请日：2011-10-24
申请人： Yuichi TERAMURA , Toshihiko OMORI , Daisuke WATANABE
发明人： Yuichi TERAMURA , Toshihiko OMORI , Daisuke WATANABE
IPC分类号： A61B5/05
CPC分类号： A61B5/0066 , A61B5/0073 , A61B5/0084 , A61B5/4244 , A61B5/425 , A61B5/6853 , A61B5/7239
摘要： A diagnosis support apparatus, includes a spatial structure data acquisition device that acquires spatial structure data including tomographic information of a three-dimensional region of an inner wall portion within a living organism that has a flat surface at a normal time that is obtained by performing optical coherence tomography measurement with respect to the inner wall portion; a surface roughness calculation device that calculates an evaluation value of a surface roughness at respective positions on the surface of the inner wall portion based on the spatial structure data; a lesion part extraction device that extracts a region of a lesion part based on a position on the surface at which the evaluation value exceeds a predetermined threshold value; and a lesion part display device that displays information showing the region of the lesion part on an image in which the spatial structure data is visualized.
摘要翻译：诊断支持装置包括：空间结构数据获取装置，其获取包括通过执行光学获得的在正常时间具有平坦表面的活体内的内壁部分的三维区域的断层信息的空间结构数据相对于内壁部分的相干断层摄影测量; 表面粗糙度计算装置，其基于所述空间结构数据计算所述内壁部的表面的各位置的表面粗糙度的评价值; 病变部分提取装置，其基于所述评估值超过预定阈值的表面上的位置提取病变部分的区域; 以及病变部显示装置，其显示在空间结构数据可视化的图像上显示病变部位的区域的信息。

5. 发明申请

US20110234252A1 WAFER UNIT FOR TESTING AND TEST SYSTEM 有权
标题翻译：用于测试和测试系统的WAFER单元
公开(公告)号：US20110234252A1
公开(公告)日：2011-09-29
申请号：US12953362
申请日：2010-11-23
申请人： Daisuke WATANABE , Toshiyuki OKAYASU
发明人： Daisuke WATANABE , Toshiyuki OKAYASU
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/2831
摘要： Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.
摘要翻译：提供了一种用于测试形成在半导体晶片上的多个半导体芯片的测试晶片单元，该测试晶片单元包括：具有对应于半导体晶片形状的形状的测试晶片; 以及形成在所述测试晶片上的多个测试电路，每个测试电路被提供以对应于所述多个半导体芯片中的两个或更多个并且测试所述两个或更多个半导体芯片。测试晶片单元可以包括与多个半导体芯片的测试端子成一一关系的在测试晶片上形成的多个连接端子，其中多个连接端子中的每一个连接到相应的一个测试端子。

6. 发明申请

US20110218752A1 TEST APPARATUS AND MANUFACTURING METHOD 有权
标题翻译：测试装置和制造方法
公开(公告)号：US20110218752A1
公开(公告)日：2011-09-08
申请号：US13044320
申请日：2011-03-09
申请人： Daisuke WATANABE , Toshiyuki OKAYASU
发明人： Daisuke WATANABE , Toshiyuki OKAYASU
IPC分类号： G06F19/00
CPC分类号： G01R31/318511 , G01R31/31926
摘要： Provided is a test apparatus that tests a plurality of devices under test formed on a wafer under test. The test apparatus comprises a test substrate that faces the wafer under test and is electrically connected to the devices under test; a programmable device that is provided on the test substrate and changes a logic relationship of output logic data with respect to input logic data, according to program data supplied thereto; a plurality of input/output circuits that are provided on the test substrate to correspond to the devices under test and that each supply the corresponding device under test with a test signal corresponding to the output logic data of the programmable device; and a judging section that judges pass/fail of each device under test, based on operation results of each device under test according to the test signal.
摘要翻译：提供了一种测试在测试晶片上形成的多个待测器件的测试装置。测试装置包括面向正在测试的晶片并与被测器件电连接的测试基板; 根据提供给其的程序数据，设置在测试基板上并根据输入逻辑数据改变输出逻辑数据的逻辑关系的可编程设备; 多个输入/输出电路，其设置在测试基板上以对应于被测器件，并且每个输入/输出电路以对应于可编程器件的输出逻辑数据的测试信号提供相应的被测器件; 以及判断部，根据测试信号，根据被测设备的运算结果判断各被测设备的通过/失败。

7. 发明申请

US20110199134A1 TEST APPARATUS, TRANSMISSION APPARATUS, RECEIVING APPARATUS, TEST METHOD, TRANSMISSION METHOD AND RECEIVING METHOD 有权
标题翻译：测试装置，传输装置，接收装置，测试方法，传输方法和接收方法
公开(公告)号：US20110199134A1
公开(公告)日：2011-08-18
申请号：US13026155
申请日：2011-02-11
申请人： Daisuke WATANABE
发明人： Daisuke WATANABE
IPC分类号： H03L7/00
CPC分类号： G01R31/31932 , G01R31/31726
摘要： Provided is a test apparatus that tests a device under test, comprising a phase comparing section that compares a phase of an internal clock generated in the test apparatus and a phase of a clock superimposed on a device signal output by the device under test; an adjusting section that adjusts a phase shift amount of the internal clock with respect to the device signal, based on the phase comparison result; an acquiring section that acquires the device signal according to the internal clock whose phase shift amount with respect to the device signal is adjusted; and an inhibiting section that inhibits change of the phase shift amount based on the phase comparison result, for at least a portion of a period during which the clock is not superimposed on the device signal. Also provided is a test method relating to the test apparatus.
摘要翻译：提供了一种测试被测设备的测试装置，包括相位比较部分，其比较测试装置中产生的内部时钟的相位和叠加在由被测器件输出的器件信号上的时钟的相位; 调整部，其根据所述相位比较结果调整所述内部时钟相对于所述装置信号的相移量; 获取部，其根据调整了相对于所述装置信号的相移量的内部时钟获取所述装置信号; 以及禁止部，其在所述时钟未叠加在所述装置信号上的周期的至少一部分期间，基于所述相位比较结果，禁止所述相位偏移量的变化。还提供了与测试装置相关的测试方法。

8. 发明申请

US20110128031A1 TEST SYSTEM AND SUBSTRATE UNIT FOR TESTING 有权
标题翻译：测试系统和底板测试单元
公开(公告)号：US20110128031A1
公开(公告)日：2011-06-02
申请号：US12953352
申请日：2010-11-23
申请人： Daisuke WATANABE , Toshiyuki OKAYASU
发明人： Daisuke WATANABE , Toshiyuki OKAYASU
IPC分类号： G01R31/26
CPC分类号： G01R31/2889
摘要： A test system that tests a plurality of chips under test formed on a wafer under test, the test system comprising a plurality of test substrates that are arranged in overlapping layers and that each have a plurality of test circuits, whose function is determined for each wafer, formed thereon; a plurality of connecting sections that electrically connect, to the chips under test, the test circuits formed on one of the test substrates; and a control apparatus that controls each of the test circuits. Each test substrate has test circuits, with a function predetermined for each substrate, formed thereon.
摘要翻译：一种在被测晶片上测试被测试的多个待测芯片的测试系统，所述测试系统包括多个测试基板，所述多个测试基板布置在重叠层中，并且每个具有多个测试电路，每个测试电路的功能是针对每个晶片，形成在其上多个连接部，其将与测试用芯片电连接的测试电路形成在一个测试基板上; 以及控制每个测试电路的控制装置。每个测试基板具有在其上形成的具有对于每个基板预定的功能的测试电路。

9. 发明申请

US20090261240A1 CALIBRATION JIG FOR OPTICAL TOMOGRAPHIC IMAGING APPARATUS AND METHOD FOR GENERATING A CALIBRATION CONVERSION TABLE 有权
标题翻译：用于光学图像成像装置的校准夹和用于产生校准转换表的方法
公开(公告)号：US20090261240A1
公开(公告)日：2009-10-22
申请号：US12496273
申请日：2009-07-01
申请人： Daisuke WATANABE , Yuichi Teramura
发明人： Daisuke WATANABE , Yuichi Teramura
IPC分类号： G01D18/00 , G01B9/02
CPC分类号： G01B9/02072 , G01B9/02004 , G01B9/0205 , G01B9/02074 , G01B9/02083 , G01B9/02091 , G01D18/00 , G06F17/17
摘要： A calibration jig allowing simple and repeatable calibration of a probe optical tomographic apparatus is disclosed. The jig includes a holding member removably attachable to an attachment section of the apparatus and a reflective surface held by the holding member. The reflective surface reflects measurement light emitted from an emitting section of the attachment section and directs reflected light back to the emitting section. If a probe of the apparatus is covered with a sheath, the jig may include a light transmitting member, which generates the same dispersion as dispersion at the sheath, between the emitting section and the reflective surface. The reflective surface may be a single reflective surface disposed within an area corresponding to twice a coherence length of the laser light with a zero path position of the reflective surface being the center of the area.
摘要翻译：公开了一种允许探针光学断层摄影装置的简单且可重复校准的校准夹具。夹具包括可移除地附接到装置的附接部分的保持构件和由保持构件保持的反射表面。反射表面反射从附接部分的发射部分发射的测量光并将反射光引导回发射部分。如果装置的探针被护套覆盖，则夹具可以包括透光构件，其在发射部分和反射表面之间产生与护套处的分散体相同的色散。反射表面可以是设置在对应于激光的相干长度的两倍的区域内的单个反射表面，反射表面的零路径位置是该区域的中心。

10. 发明申请

US20160254442A1 MAGNETORESISTIVE MEMORY DEVICE 有权
标题翻译：磁记忆体设备
公开(公告)号：US20160254442A1
公开(公告)日：2016-09-01
申请号：US14814158
申请日：2015-07-30
申请人： Kazuya SAWADA , Toshihiko NAGASE , Youngmin EEH , Koji UEDA , Daisuke WATANABE , Makoto NAGAMINE
发明人： Kazuya SAWADA , Toshihiko NAGASE , Youngmin EEH , Koji UEDA , Daisuke WATANABE , Makoto NAGAMINE
IPC分类号： H01L43/08 , H01L43/10 , H01L43/02
CPC分类号： H01L43/08 , H01L27/228 , H01L43/10
摘要： According to one embodiment, a magnetoresistive memory device includes a first magnetic layer, a second magnetic layer, a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and a third magnetic layer provided on a side of the first or second magnetic layer opposite to the nonmagnetic layer. The third magnetic layer has a multilayer film having an artificial lattice structure, and the third magnetic layer is partly microcrystalline or amorphous.
摘要翻译：根据一个实施例，磁阻存储器件包括第一磁性层，第二磁性层，设置在第一磁性层和第二磁性层之间的非磁性层，以及设置在第一或第二磁性层的一侧的第三磁性层层与非磁性层相对。第三磁性层具有具有人造晶格结构的多层膜，第三磁性层是部分微晶或无定形的。

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