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1. 发明授权

US4985827A Computer for synchronized read and write of vector data 失效
标题翻译：用于同步读写矢量数据的计算机
公开(公告)号：US4985827A
公开(公告)日：1991-01-15
申请号：US226376
申请日：1988-07-29
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima , Junji Nakagoshi , Kazuo Ojima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F17/16 , G06F15/78 , G06F15/80
CPC分类号： G06F15/8092 , G06F15/8084
摘要： A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

2. 发明授权

US5867679A Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor employing controlled execution of a program by the data using processor for processing the data 失效
标题翻译：并行处理器系统，其通过数据产生处理器将异步数据传输到使用处理器的数据的数据采用由数据使用处理器处理数据的数据的受控执行程序
公开(公告)号：US5867679A
公开(公告)日：1999-02-02
申请号：US647773
申请日：1991-01-30
申请人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
发明人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F9/44 , G06F15/17 , G06F15/80 , G06F15/82
CPC分类号： G06F15/8015 , G06F9/4494 , G06F15/17
摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
摘要翻译：并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

3. 发明授权

US5010477A Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations 失效
标题翻译：用于在并行处理系统与用于处理器间数据通信的寄存器和逻辑之间传送矢量数据的方法和装置独立于处理操作
公开(公告)号：US5010477A
公开(公告)日：1991-04-23
申请号：US109293
申请日：1987-10-15
申请人： Koichiro Omoda , Teruo Tanaka , Junji Nakagoshi , Naoki Hamanaka , Shigeo Nagashima
发明人： Koichiro Omoda , Teruo Tanaka , Junji Nakagoshi , Naoki Hamanaka , Shigeo Nagashima
IPC分类号： G06F15/80
CPC分类号： G06F15/8092 , G06F15/8015
摘要： A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.
摘要翻译：具有多个处理器单元的并行处理器系统包括：传送信息生成电路，用于通过向矢量数据添加用于矢量数据的数据标识符和目的处理器单元号来生成传送信息，发送电路，用于将传送信息发送到数据通信路径，用于保持从数据通信路径发送的传送信息的接收电路，以及用于基于由传送信息生成电路产生的数据标识符从接收电路连续读取相关元素数据的向量寄存器。

4. 发明授权

US5086498A Parallel computer with asynchronous communication facility 失效
标题翻译：具有异步通信设备的并行计算机
公开(公告)号：US5086498A
公开(公告)日：1992-02-04
申请号：US145614
申请日：1988-01-10
申请人： Teruo Tanaka , Naoki Hamanaka , Junji Nakagoshi , Koichiro Omoda , Shigeo Nagashima
发明人： Teruo Tanaka , Naoki Hamanaka , Junji Nakagoshi , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F15/17 , G06F15/173 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8092 , G06F15/17 , G06F15/173
摘要： In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.
摘要翻译：在多处理器数字计算机系统ID数据中，与期望的处理器间通信的数据相耦合，从一个处理器传送并暂时保存在接收处理器中的接收缓冲器（关联存储器）中的数据。该ID被划分为主ID数据MK和子ID数据SK。主ID数据MK用于从接收缓冲器搜索数据。子ID数据SK用作接收处理器中的数据的ID。

5. 发明授权

US5465380A Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs 失效
标题翻译：使用程序的唯一标识符在不同处理器中的相同程序组的程序之间传送数据的数据传输方法
公开(公告)号：US5465380A
公开(公告)日：1995-11-07
申请号：US222949
申请日：1994-04-04
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F9/46 , G06F15/16 , G06F9/00
CPC分类号： G06F9/54 , G06F15/161
摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.
摘要翻译：一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

6. 发明授权

US5301322A System for converting job/process identifiers into processor/process identifiers in transferring data between processes in a multiprocessor system 失效
标题翻译：用于将作业/过程标识符转换为处理器/进程标识符的系统，用于在多处理器系统中的进程之间传送数据
公开(公告)号：US5301322A
公开(公告)日：1994-04-05
申请号：US912215
申请日：1992-07-10
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F9/46 , G06F15/16 , G06F9/00
CPC分类号： G06F9/54 , G06F15/161
摘要： A parallel processor system includes a transfer circuit and a plurality of processors each of which executes at least one of a plurality of mutually associated programs. The transfer circuit transfers data from a sending program allotted to one processor to a receiving program allotted to another processor by identifying the other processor and the receiving program based on a job number and within-job process number outputted by the sending program.
摘要翻译：并行处理器系统包括传送电路和多个处理器，每个处理器执行多个相互关联的程序中的至少一个。传送电路根据发送程序输出的作业号和作业内编号，通过识别其他处理器和接收程序，将数据从分配给一个处理器的发送程序传送到分配给另一个处理器的接收程序。

7. 发明授权

US5113390A Data transfer network suitable for use in a parallel computer 失效
标题翻译：数据传输网络适用于并行计算机
公开(公告)号：US5113390A
公开(公告)日：1992-05-12
申请号：US508065
申请日：1990-04-10
申请人： Takehisa Hayashi , Koichiro Omoda , Teruo Tanaka , Naoki Hamanaka , Shigeo Nagashima
发明人： Takehisa Hayashi , Koichiro Omoda , Teruo Tanaka , Naoki Hamanaka , Shigeo Nagashima
IPC分类号： H04L12/935 , H04L12/937
CPC分类号： H04L49/3018 , H04L49/254 , H04L49/3027
摘要： A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer. The network includes a plurality of multistage switches each belonging to one of plural stages and connected to the switches of a preceding stage and to switches of the succeeding stage. Each of the switches are arranged to receive packets from a preceding switch. A packet includes a target process address and data to be transferred. A path select device is connected to receive packets and is also connected to plural switches belonging to a next stage for the transfer of the received partial addresses and partial data. A control device is connected to receive the partial addresses and partial data and is responsive to a predetermined bit within the received partial addresses. The control means is responsive to the arrival of the first partial address of the packet.

8. 发明授权

US5742766A Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof 失效
标题翻译：并行计算系统，用于通过使用部分开关电路来同步处理器，用于在接收同步信号之后广播消息并且判断其同步
公开(公告)号：US5742766A
公开(公告)日：1998-04-21
申请号：US34805
申请日：1993-03-19
申请人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
发明人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
IPC分类号： G06F9/52 , G06F15/173 , G06F15/80 , G06F13/12
CPC分类号： G06F15/17343 , G06F15/17381
摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
摘要翻译：来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

9. 发明授权

US5826049A Partial broadcast method in parallel computer and a parallel computer suitable therefor 失效
标题翻译：并行计算机中的部分广播方法和适用于其的并行计算机
公开(公告)号：US5826049A
公开(公告)日：1998-10-20
申请号：US916630
申请日：1992-07-22
申请人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
发明人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
IPC分类号： G06F15/173 , G06F15/80 , G06F15/163
CPC分类号： G06F15/17368
摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.
摘要翻译：为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。为了定义接收端处理器组的范围，网络包括传送控制电路。交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此特定的部分广播消息从相同的输出端口传送。

10. 发明授权

US5754792A Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same 失效
标题翻译：由用于并行传送消息的逻辑分割开关组成的开关电路和使用该开关的并行处理器系统
公开(公告)号：US5754792A
公开(公告)日：1998-05-19
申请号：US34359
申请日：1993-03-19
申请人： Shinichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Shigeo Takeuchi , Teruo Tanaka
发明人： Shinichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Shigeo Takeuchi , Teruo Tanaka
IPC分类号： G06F11/14 , G06F15/173 , H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： G06F15/17375 , G06F11/1443 , H04L49/1576 , H04L49/256 , H04Q11/0478
摘要： A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.
摘要翻译：一种并行处理器系统，包括多个处理器。当从不同的端口输入相同的目的地PE号码的分组时，通过使用各自的加法电路，分别将目的地PE号码分别与不同的输入端口所属的分离的交叉开关的前导端口的ID号相加，从而确定传送目标输出端口为数据包。通过划分交叉开关来实现具有不同数量的输入/输出端口的多个分开的交叉开关。通过与每个输出端口相关联地提供的输入端口选择电路，接收来自属于相关联的输出端口所属的分离交叉开关的输入端口的分组的输出请求，同时对分组的输出请求从属于其他分割交叉开关的输入端口被禁止被接受，从而在属于物理上相同的交叉开关的分开的交叉开关之间禁止广播分组的传送。可以避免这种情况，其中相同的广播分组多次到达同一个处理器。

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