专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08296258B2 Automated channel market data extraction, validation and transformation 有权
标题翻译：自动化渠道市场数据提取，验证和转型
公开(公告)号：US08296258B2
公开(公告)日：2012-10-23
申请号：US12130582
申请日：2008-05-30
申请人： Nahum Rand , Vineet Joshi , Irwin Rosenblum
发明人： Nahum Rand , Vineet Joshi , Irwin Rosenblum
IPC分类号： G06F15/16
CPC分类号： G06Q30/06
摘要： Select portions of product channel data collected by a product channel participant and stored in a data warehouse are periodically extracted based on a previously determined template. The extracted subset of product channel data is thereafter transformed so that the format of the data complies with that of the requesting enterprise. Once transformed, one or more rule sets is applied to the subset of transformed data to guarantee that the information complies with requirements set forth by the enterprise yet does not violate any disclosure rules of the product channel participant. Thereafter and on a scheduled basis, the transformed and validated data is delivered to a delivery server from which the enterprise can retrieve the data at its convenience.
摘要翻译：基于先前确定的模板，周期性地提取选择由产品通道参与者收集并存储在数据仓库中的产品通道数据的部分。然后，将所提取的产品通道数据子集进行转换，使得数据格式符合请求企业的格式。一旦转换，一个或多个规则集被应用于转换数据的子集，以保证信息符合企业提出的要求，但不违反产品渠道参与者的任何披露规则。此后，按照计划，转换和验证的数据将传送到一个交付服务器，企业可以从该服务器方便地检索数据。

2. 发明申请

US20090327452A1 AUTOMATED CHANNEL DATA EXTRACTION AND TRANSFORMATION 有权
标题翻译：自动通道数据提取和转换
公开(公告)号：US20090327452A1
公开(公告)日：2009-12-31
申请号：US12130582
申请日：2008-05-30
申请人： Nahum Rand , Vineet Joshi , Irwin Rosenblum
发明人： Nahum Rand , Vineet Joshi , Irwin Rosenblum
IPC分类号： G06F15/16
CPC分类号： G06Q30/06
摘要： Select portions of product channel data collected by a product channel participant and stored in a data warehouse are periodically extracted based on a previously determined template. The extracted subset of product channel data is thereafter transformed so that the format of the data complies with that of the requesting enterprise. Once transformed, one or more rule sets is applied to the subset of transformed data to guarantee that the information complies with requirements set forth by the enterprise yet does not violate any disclosure rules of the product channel participant. Thereafter and on a scheduled basis, the transformed and validated data is delivered to a delivery server from which the enterprise can retrieve the data at its convenience.
摘要翻译：基于先前确定的模板，周期性地提取选择由产品通道参与者收集并存储在数据仓库中的产品通道数据的部分。然后，将所提取的产品通道数据子集进行转换，使得数据格式符合请求企业的格式。一旦转换，一个或多个规则集被应用于转换数据的子集，以保证信息符合企业提出的要求，但不违反产品渠道参与者的任何披露规则。此后，按照计划，转换和验证的数据将传送到一个交付服务器，企业可以从该服务器方便地检索数据。

3. 发明申请

US20080300987A1 WEBSITE MONETIZATION 审中-公开
标题翻译：网站制衡
公开(公告)号：US20080300987A1
公开(公告)日：2008-12-04
申请号：US12130698
申请日：2008-05-30
申请人： Nahum Rand , Vineet Joshi
发明人： Nahum Rand , Vineet Joshi
IPC分类号： G06Q30/00 , G01S5/00
CPC分类号： G06Q30/06 , G06Q30/0239 , G06Q30/0601
摘要： A merchant portal accessible by a user via the Internet searches for a product using typical search techniques. The merchant portal returns to the user a list of merchants in an identified geographic location. For each listed merchant, a token is created that associates the inquiry and the merchant. Once a token has been generated, financial transactions at the merchant are monitored for the time corresponding to the life of the token. When a transaction occurs at a merchant involving the user, a report is generated associating that sale with the inquiry. Based on the sale, a fee for directing the user to the merchant is generated.
摘要翻译：用户可以通过互联网访问的商业门户使用典型的搜索技术搜索产品。商户门户向用户返回所识别的地理位置中的商家列表。对于每个列出的商家，创建将查询与商家相关联的令牌。一旦生成了令牌，商家的金融交易将在与令牌的寿命相对应的时间内进行监控。当涉及用户的商家发生交易时，生成将该销售与查询相关联的报告。基于销售，产生用于指导用户到商家的费用。

4. 发明授权

US08201033B2 Memory having an ECC system 有权
标题翻译：具有ECC系统的存储器
公开(公告)号：US08201033B2
公开(公告)日：2012-06-12
申请号：US13174018
申请日：2011-06-30
申请人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
发明人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
摘要翻译：提供了一种用于存储器的纠错码系统。存储器具有可直接访问的奇偶校验阵列。纠错码系统的一个实施例包括将测试数据直接写入并读取到奇偶校验阵列。将从奇偶校验阵列读取的数据与写入奇偶校验阵列的测试数据进行比较，以检测错误。

5. 发明申请

US20100281302A1 Memory Having an ECC System 有权
标题翻译：具有ECC系统的内存
公开(公告)号：US20100281302A1
公开(公告)日：2010-11-04
申请号：US12833613
申请日：2010-07-09
申请人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
发明人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
IPC分类号： G06F11/263
CPC分类号： G06F11/1048
摘要： An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
摘要翻译：提供了一种用于存储器的纠错码系统。存储器具有可直接访问的奇偶校验阵列。纠错码系统的一个实施例包括将测试数据直接写入并读取到奇偶校验阵列。将从奇偶校验阵列读取的数据与写入奇偶校验阵列的测试数据进行比较，以检测错误。

6. 发明授权

US07996734B2 Memory having an ECC system 有权
标题翻译：具有ECC系统的存储器
公开(公告)号：US07996734B2
公开(公告)日：2011-08-09
申请号：US12833613
申请日：2010-07-09
申请人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
发明人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
摘要翻译：提供了一种用于存储器的纠错码系统。存储器具有可直接访问的奇偶校验阵列。纠错码系统的一个实施例包括将测试数据直接写入并读取到奇偶校验阵列。将从奇偶校验阵列读取的数据与写入奇偶校验阵列的测试数据进行比较，以检测错误。

7. 发明申请

US20110258515A1 Memory Having an ECC System 有权
标题翻译：具有ECC系统的内存
公开(公告)号：US20110258515A1
公开(公告)日：2011-10-20
申请号：US13174018
申请日：2011-06-30
申请人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
发明人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048
摘要： An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
摘要翻译：提供了一种用于存储器的纠错码系统。存储器具有可直接访问的奇偶校验阵列。纠错码系统的一个实施例包括将测试数据直接写入并读取到奇偶校验阵列。将从奇偶校验阵列读取的数据与写入奇偶校验阵列的测试数据进行比较，以检测错误。

8. 发明授权

US07779334B2 Memory having an ECC system 有权
标题翻译：具有ECC系统的存储器
公开(公告)号：US07779334B2
公开(公告)日：2010-08-17
申请号：US11767689
申请日：2007-06-25
申请人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
发明人： Adrian Earle , Raviprakrash S. Rao , Vineet Joshi
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.
摘要翻译：提供了一种用于具有位于存储器阵列内的存储器阵列的奇偶校验列的存储器的纠错码系统。奇偶校验列被分组在一起或分布在整个存储器阵列中。一个实施例包括一个多路复用器电路，用于选择性地仅将存储在奇偶校验存储器阵列中的奇偶校验位与I / O电路相耦合，绕过ECC逻辑电路，并允许奇偶校验位在直接访问模式下直接访问，或者用于选择性地将奇偶位以ECC模式的ECC逻辑电路。

9. 发明申请

US20080016392A1 ECC SYSTEM FOR MEMORY 有权
标题翻译：内存ECC系统
公开(公告)号：US20080016392A1
公开(公告)日：2008-01-17
申请号：US11767689
申请日：2007-06-25
申请人： Adrian Earl , Raviprakrash Rao , Vineet Joshi
发明人： Adrian Earl , Raviprakrash Rao , Vineet Joshi
IPC分类号： G06F11/20
CPC分类号： G06F11/1048
摘要： An error correction code system for a memory for improving performance and testability. The parity columns of the memory array can be positioned centrally within the array to minimize routing distance to ECC logic circuitry. The parity columns can be grouped together or distributed throughout the array to optimize performance. A multiplexor circuit can be included for selectively coupling only the parity bits stored in the parity memory array to I/O circuitry. Therefore, the parity columns can be directly tested, and testing of the ECC logic circuitry is facilitated.
摘要翻译：用于提高性能和可测试性的存储器的纠错码系统。存储器阵列的奇偶校验列可以集中在阵列内，以最小化到ECC逻辑电路的路由距离。奇偶校验列可以组合在一起或分布在整个阵列中以优化性能。可以包括多路复用器电路，用于仅选择性地将存储在奇偶校验存储器阵列中的奇偶校验位耦合到I / O电路。因此，可以直接测试奇偶校验列，便于ECC逻辑电路的测试。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式