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1. 发明授权

US08001508B1 Method and system for analyzing input/output simultaneous switching noise 有权
标题翻译：分析输入/输出同时开关噪声的方法和系统
公开(公告)号：US08001508B1
公开(公告)日：2011-08-16
申请号：US11877072
申请日：2007-10-23
申请人： Nafira Daud , Geping Liu , San Wong , Lawrence David Smith
发明人： Nafira Daud , Geping Liu , San Wong , Lawrence David Smith
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5072 , G06F2217/40 , G06F2217/82
摘要： A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.
摘要翻译：提供了一种用于优化集成电路的引脚选择的方法。引脚位置映射到向量。集成电路引脚之间的互感关系被捕获到矩阵中。矩阵包含每个引脚的信号状态如何影响I / O bank中其他引脚的切换的数据。将引脚位置和串扰矩阵组合起来，以表征引脚上串扰对引脚布置的影响。此后，用户可以决定改变引脚布置或改变引脚的采样间隔，以避免在串扰可能影响信号完整性时对引脚进行采样。该方法可以应用于影响信号完整性的多个同时开关噪声原因机制。在该实施例中，通过比较每个原因机制的影响来确定来自单独量化的原因机制的最坏情况引起机制。

2. 发明授权

US07683659B1 Integrated circuits with jitter-reducing balancing logic 有权
标题翻译：具有抖动平衡逻辑的集成电路
公开(公告)号：US07683659B1
公开(公告)日：2010-03-23
申请号：US12060791
申请日：2008-04-01
申请人： Iliya G. Zamek , Nafira Daud , Peter Boyle , Eugene V. Gomez
发明人： Iliya G. Zamek , Nafira Daud , Peter Boyle , Eugene V. Gomez
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00369 , G06F2217/82
摘要： Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.
摘要翻译：集成电路包含使用电源信号供电的核心逻辑。核心逻辑包含同时开关电路。同时开关电路有助于电源信号上的噪声。可以在集成电路上提供平衡电路以补偿核心逻辑中的同时开关电路。平衡电路可以接收相对于核心逻辑的输入而异相的输入信号。由于平衡电路与核心逻辑的同时开关电路异相切换，所以来自核心逻辑的噪声贡献被补偿并且电源信号上的电源噪声被最小化。

3. 发明授权

US07454301B1 Method and apparatus for predicting system noise 有权
标题翻译：用于预测系统噪声的方法和装置
公开(公告)号：US07454301B1
公开(公告)日：2008-11-18
申请号：US11465725
申请日：2006-08-18
申请人： Nafira Daud , Iliya G. Zamek , Peter Boyle
发明人： Nafira Daud , Iliya G. Zamek , Peter Boyle
IPC分类号： H03K1/04
CPC分类号： G01R31/31709 , H04L1/205
摘要： A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.
摘要翻译：提供了包括核心效果模块，输入/输出（I / O）模块和锁相环（PLL）模块）的抖动计算器引擎。核心效应模块估计由影响核心时钟网络的噪声影响引起的核心抖动。 I / O模块估计I / O输入引脚切换对时钟网络输入信号的影响。在一个实施例中，I / O模块识别在电路设计中由I / O引脚切换的相对频率。 PLL模块估计PLL对从I / O引脚传送到PLL的信号的影响。 PLL模块考虑到I / O输入引脚切换效应和内核抖动。抖动计算器引擎可以与数据库通信，并且评估的不同设计可以存储在数据库中，使得数据库成为不同设计的存储库，并且可以为将来的设计提供有用的信息。

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