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1. 发明授权

US10656952B2 System on chip (SOC) and method for handling interrupts while executing multiple store instructions 有权
公开(公告)号：US10656952B2
公开(公告)日：2020-05-19
申请号：US14702612
申请日：2015-05-01
申请人： NXP B.V.
发明人： Nicolas Laine , Cyril Edeline
IPC分类号： G06F9/30 , G06F9/38 , G06F13/24 , G06F13/12
摘要： A processor circuit is disclosed. In an embodiment, the processor circuit includes a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words, and a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.

2. 发明申请

US20150317164A1 CONTROLLER CIRCUITS, DATA INTERFACE BLOCKS, AND METHODS FOR TRANSFERRING DATA 审中-公开
标题翻译：控制器电路，数据接口块和传输数据的方法
公开(公告)号：US20150317164A1
公开(公告)日：2015-11-05
申请号：US14702612
申请日：2015-05-01
申请人： NXP B.V.
发明人： Nicolas Laine , Cyril Edeline
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30043
摘要： A processor circuit, with: a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words; a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.
摘要翻译：一种处理器电路，具有：处理器单元，被配置为执行用于加载或存储多个数据字的多重加载或多个存储指令; 数据接口块DIB，被配置为与处理器通信并且被配置为响应于在执行多个加载或存储指令期间发生中断，保存多个加载或存储指令的状态。保存状态可以包括存储当中断发生时已经加载或存储的数据字的数量。当中断后再次执行多次加载/存储指令时，DIB可以跳过存储的数据字数。

3. 发明申请

US20140149643A1 PATCH MECHANISM IN EMBEDDED CONTROLLER FOR MEMORY ACCESS 审中-公开
标题翻译：嵌入式控制器中的存储机制用于存储器访问
公开(公告)号：US20140149643A1
公开(公告)日：2014-05-29
申请号：US13866358
申请日：2013-04-19
申请人： NXP B.V.
发明人： Raymond Devinoy , Nicolas Laine
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F8/66
摘要： Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.
摘要翻译：各种示例性实施例涉及连接在数据总线和ROM存储器控制器之间的补丁模块。补丁模块可以包括：配置为存储ROM地址的至少一个补丁地址寄存器; 对应于每个补丁地址寄存器的补丁数据寄存器，每个补丁数据寄存器被配置用于存储指令; 地址比较器，被配置为将数据总线上接收的地址与存储在每个补丁地址寄存器中的地址进行比较，并输出标识匹配补丁地址寄存器的第一信号和指示是否存在匹配地址的第二信号; 以及第一多路复用器，被配置为选择对应于匹配补丁地址寄存器的补丁数据寄存器，并将补丁数据寄存器的内容输出到数据总线。

4. 发明授权

US10824552B2 Patch mechanism in embedded controller for memory access 有权
公开(公告)号：US10824552B2
公开(公告)日：2020-11-03
申请号：US13866358
申请日：2013-04-19
申请人： NXP B.V.
发明人： Raymond Devinoy , Nicolas Laine
IPC分类号： G06F12/02 , G06F8/65
摘要： Various exemplary embodiments relate to a patch module connected between a data bus and a ROM memory controller. The patch module may include: at least one patch address register configured to store a ROM address; a patch data register corresponding to each patch address register, each patch data register configured for storing an instruction; an address comparator configured to compare an address received on the data bus with an address stored in each patch address register and output a first signal identifying a matching patch address register and a second signal indicating whether there is a matching address; and a first multiplexer configured to select the patch data register corresponding to the matching patch address register and output the contents of the patch data register to the data bus.

5. 发明授权

US09355276B2 Processing system 有权
标题翻译：处理系统
公开(公告)号：US09355276B2
公开(公告)日：2016-05-31
申请号：US14258933
申请日：2014-04-22
申请人： NXP B.V.
发明人： Nicolas Laine , Andre Lepine
IPC分类号： G06F21/00 , G06F21/62 , G06F21/14 , G06F21/79 , G06F21/57
CPC分类号： G06F21/629 , G06F21/14 , G06F21/572 , G06F21/79
摘要： A processing system is disclosed. The system comprises: a processing unit; a memory adapted to store firmware code and application code for execution by the processor; and a memory access control unit adapted to control access of the processing unit to firmware code and application code stored in the memory. The memory access control unit is adapted to disable access to firmware code when access to application code is enabled, and to disable access to application code when access to firmware code is enabled.
摘要翻译：公开了一种处理系统。该系统包括：处理单元; 存储器，适于存储固件代码和用于由处理器执行的应用代码; 以及存储器访问控制单元，其适于控制处理单元对存储在存储器中的固件代码和应用代码的访问。存储器访问控制单元适于在启用对应用代码的访问时禁用对固件代码的访问，并且当启用访问固件代码时禁用对应用代码的访问。

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