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1. 发明授权

US09110141B2 Flip-flop circuit having a reduced hold time requirement for a scan input 有权
标题翻译：对于扫描输入，具有减小的保持时间要求的触发器电路
公开(公告)号：US09110141B2
公开(公告)日：2015-08-18
申请号：US13668143
申请日：2012-11-02
申请人： NVIDIA Corporation
发明人： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Jiani Yu , Ting-Hsiang Chu
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318541 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318594
摘要： A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.
摘要翻译：扫描触发电路包括扫描输入子电路和选择子电路。扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号信号在两个不同的逻辑电平之间。选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相版本输出为第一选择输入信号。

2. 发明申请

US20140125377A1 DUAL FLIP-FLOP CIRCUIT 有权
标题翻译：双浮点电路
公开(公告)号：US20140125377A1
公开(公告)日：2014-05-08
申请号：US13668110
申请日：2012-11-02
申请人： NVIDIA CORPORATION
发明人： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Jiani Yu , Ting-Hsiang Chu
IPC分类号： H03K19/0175 , H03K19/00
CPC分类号： H03K3/356156 , G01R31/318541 , H03K3/356121
摘要： A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.
摘要翻译：双触发器电路将两个或更多个触发器子电路组合成单个电路。触发器电路包括第一触发器子电路和第二触发器子电路。第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号，被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定的输入信号传送到第二输出信号。

3. 发明申请

US20140129887A1 FLIP-FLOP CIRCUIT HAVING A REDUCED HOLD TIME REQUIREMENT FOR A SCAN INPUT 有权
标题翻译：对于扫描输入，具有减少保持时间要求的FLIP-FLOP电路
公开(公告)号：US20140129887A1
公开(公告)日：2014-05-08
申请号：US13668143
申请日：2012-11-02
申请人： NVIDIA CORPORATION
发明人： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Jiani Yu , Ting-Hsiang Chu
IPC分类号： G01R31/3177
CPC分类号： G01R31/318541 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318594
摘要： A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.
摘要翻译：扫描触发电路包括扫描输入子电路和选择子电路。扫描输入子电路被配置为接收扫描输入信号和扫描使能信号，并且当扫描使能信号被激活时，产生表示相对于时钟输入的转变而被延迟的扫描输入信号的互补扫描输入信号信号在两个不同的逻辑电平之间。选择子电路耦合到扫描输入子电路并且被配置为接收互补扫描输入信号，并且基于扫描使能信号，将扫描输入信号或数据信号的反相形式输出为第一选择输入信号。

4. 发明授权

US08866528B2 Dual flip-flop circuit 有权
标题翻译：双触发器电路
公开(公告)号：US08866528B2
公开(公告)日：2014-10-21
申请号：US13668110
申请日：2012-11-02
申请人： NVIDIA Corporation
发明人： Hwong-Kwo Lin , Ge Yang , Xi Zhang , Jiani Yu , Ting-Hsiang Chu
IPC分类号： H03K3/289
CPC分类号： H03K3/356156 , G01R31/318541 , H03K3/356121
摘要： A dual flip-flop circuit combines two or more flip-flip sub-circuits into a single circuit. The flip-flop circuit comprises a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub-circuit comprises a first storage sub-circuit configured to store a first selected input signal and transfer the first selected input signal to a first output signal when a buffered clock signal transitions between two different logic levels and a dock driver configured to receive a clock input signal, generate an inverted clock signal, and generate the buffered clock signal. The second flip-flop sub-circuit is coupled to the clock driver and configured to receive the inverted clock signal and the buffered clock signal. The second flip-flop sub-circuit comprises a second storage sub-circuit configured to store a second selected input signal and transfer the second selected input signal to a second output signal when the buffered clock signal transitions.
摘要翻译：双触发器电路将两个或更多个触发器子电路组合成单个电路。触发器电路包括第一触发器子电路和第二触发器子电路。第一触发器子电路包括第一存储子电路，其被配置为存储第一选择的输入信号，并且当缓冲的时钟信号在两个不同逻辑电平之间转换时，将第一选定的输入信号传送到第一输出信号，被配置为接收时钟输入信号，产生反相时钟信号，并产生缓冲的时钟信号。第二触发器子电路耦合到时钟驱动器并且被配置为接收反相时钟信号和经缓冲的时钟信号。第二触发器子电路包括第二存储子电路，其被配置为存储第二选择的输入信号，并且在缓冲的时钟信号转换时将第二选定输入信号传送到第二输出信号。

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