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1. 发明授权

US06870742B2 System board 有权
标题翻译：系统板
公开(公告)号：US06870742B2
公开(公告)日：2005-03-22
申请号：US10200731
申请日：2002-07-22
申请人： Myun-Joo Park , Byung-Se So , Sang-Won Lee , Jae-Jun Lee
发明人： Myun-Joo Park , Byung-Se So , Sang-Won Lee , Jae-Jun Lee
IPC分类号： G06F1/18 , G06F3/06 , G06F13/14 , H05K1/02 , H05K7/06
CPC分类号： H05K1/0248 , H05K2201/044 , H05K2201/09236 , H05K2201/09254
摘要： A system board includes a control unit; connectors arranged in series in one direction and accepting a connecting means for inputting and outputting data; and signal lines connecting the control unit to the connectors and including at least one branch point, wherein sub signal lines branched off at the same branch point are equal in length and/or loads of path from the branch point to the connecting means.
摘要翻译：系统板包括控制单元; 连接器在一个方向上串联布置并且接受用于输入和输出数据的连接装置; 以及将控制单元连接到连接器并且包括至少一个分支点的信号线，其中在相同分支点处分支的子信号线在从分支点到连接装置的路径的长度和/或负载相等。

2. 发明授权

US07254675B2 Memory system having memory modules with different memory device loads 有权
标题翻译：具有不同存储器件负载的存储器模块的存储器系统
公开(公告)号：US07254675B2
公开(公告)日：2007-08-07
申请号：US10629866
申请日：2003-07-30
申请人： Jae-Jun Lee , Byung-Se So , Myun-Joo Park
发明人： Jae-Jun Lee , Byung-Se So , Myun-Joo Park
IPC分类号： G06F12/00
CPC分类号： G06F13/4086
摘要： A memory system system includes a single in-line memory module (SIMM) which contains a memory device and a signal transmission line connected between the memory device and a connection terminal, and a dual in-line memory module (DIMM) which contains two memory devices and a signal transmission line connected between the two memory devices and a connection terminal. A length of the signal transmission line of the SIMM is longer than a length of the signal transmission line of the DIMM. The load of the memory device of the SIMM is less than the load of memory devices of the DIMM, and the longer length of the signal transmission line of the SIMM increases a signal delay time of the SIMM to compensate for the different loads of the SIMM and DIMM memory devices. The longer length of the signal transmission line of the SIMM may further compensate for a signal transmission line connected between the first and second sockets which receive the SIMM and DIMM, respectively.
摘要翻译：一种存储系统系统包括一个单一的在线存储器模块（SIMM），它包含连接在存储器件和连接端子之间的存储器件和信号传输线，以及包含两个存储器的双列直插存储器模块（DIMM）设备和连接在两个存储设备和连接终端之间的信号传输线。 SIMM的信号传输线的长度长于DIMM的信号传输线的长度。 SIMM的存储器件的负载小于DIMM的存储器件的负载，并且SIMM的信号传输线的较长的长度增加了SIMM的信号延迟时间以补偿SIMM的不同负载和DIMM存储设备。 SIMM的信号传输线的较长的长度可进一步补偿连接在接收SIMM和DIMM的第一和第二插座之间的信号传输线。

3. 发明授权

US07215561B2 Semiconductor memory system having multiple system data buses 有权
标题翻译：具有多个系统数据总线的半导体存储器系统
公开(公告)号：US07215561B2
公开(公告)日：2007-05-08
申请号：US10644735
申请日：2003-08-21
申请人： Myun-Joo Park , Byung-Se So , Jae-Jun Lee
发明人： Myun-Joo Park , Byung-Se So , Jae-Jun Lee
IPC分类号： G11C5/00 , G11C8/00
CPC分类号： G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： The semiconductor memory system includes a memory controller, N system data buses, and first through P-th memory module groups. The N system data buses are connected to the memory controller and respectively have a width of M/N bits. The first through P-th memory module groups are connected to the N system data buses and respectively have N memory modules. In each of the first through P-th memory module groups, a different one of the N system data buses is connected to each of the N memory modules, and each of the N system data buses has a data bus width of M/N bits. The first through P-th memory module groups are operated in response to first through P-th corresponding chip select signals. M is the bit-width of an entire system data bus of the semiconductor memory system. The N system data buses are wired such that data transmission times are the same from each N memory modules that operate in response to the same chip select signal to the memory controller.
摘要翻译：半导体存储器系统包括存储器控制器，N个系统数据总线以及第一到第P个存储器模块组。 N个系统数据总线连接到存储器控制器，并且分别具有M / N位的宽度。第一至第P存储器模块组连接到N个系统数据总线，并分别具有N个存储器模块。在第一到第P存储器模块组中的每一个中，N个系统数据总线中的不同的一个连接到N个存储器模块中的每一个，并且N个系统数据总线中的每一个具有M / N位的数据总线宽度。响应于第一至第P对应的芯片选择信号操作第一到第P个存储器模块组。 M是半导体存储器系统的整个系统数据总线的位宽。 N系统数据总线被布线，使得数据传输时间与从存储器控制器的相同芯片选择信号响应的每个N个存储器模块相同。

4. 发明授权

US06828819B2 High-speed memory system 有权
标题翻译：高速内存系统
公开(公告)号：US06828819B2
公开(公告)日：2004-12-07
申请号：US10353924
申请日：2003-01-30
申请人： Myun-Joo Park , Byung-Se So , Jae-Jun Lee
发明人： Myun-Joo Park , Byung-Se So , Jae-Jun Lee
IPC分类号： H03K1716
CPC分类号： G06F13/4086 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , H05K1/023 , H05K1/14
摘要： A memory system includes a chipset mounted on a circuit board, and first and second memory module connectors mounted respectively on the circuit board. The first and second memory modules are inserted into the first and second memory module connectors, respectively. The memory system further includes a bus connected to the chipset and the first and second memory module connectors so to create a branch point. Each of the first and second memory modules includes at least one memory device connected to the bus via a stub line and a stub resistor. Impedance of the bus is less than that of the stub line.
摘要翻译：存储器系统包括安装在电路板上的芯片组，以及分别安装在电路板上的第一和第二存储器模块连接器。第一和第二存储器模块分别插入到第一和第二存储器模块连接器中。存储器系统还包括连接到芯片组的总线和第一和第二存储器模块连接器，以便产生分支点。第一和第二存储器模块中的每一个包括经由短截线和短截线电阻连接到总线的至少一个存储器件。公交车的阻力小于短线的阻力。

5. 发明申请

US20080030286A1 SEMICONDUCTOR MEMORY DEVICE WITH DATA BUS SCHEME FOR REDUCING HIGH FREQUENCY NOISE 审中-公开
标题翻译：具有数据总线方案的半导体存储器件，用于降低高频噪声
公开(公告)号：US20080030286A1
公开(公告)日：2008-02-07
申请号：US11755791
申请日：2007-05-31
申请人： Myun-Joo Park , Jae-jun LEE
发明人： Myun-Joo Park , Jae-jun LEE
IPC分类号： H01P5/12
CPC分类号： H05K1/0216 , G11C7/1006 , H05K1/0237 , H05K1/14 , H05K2201/044 , H05K2201/09727 , H05K2201/09781
摘要： A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.
摘要翻译：半导体存储器件包括具有存储器的存储器模块和将数据传送到存储器模块的数据总线，其中数据总线包括一个低频带数据传递单元，该单元去除数据的高频分量并将数据发送到内存模块低频带数据传送单元包括并联连接到数据总线并形成为印刷电路板（PCB）图案的多个短截线。低频带数据传送单元包括并联连接到数据总线并形成为PCB图案的多个板。低频带数据传送单元具有宽度宽的部分和宽度窄的部分交替连接的形状。因此，在不添加单独的无源器件的情况下，半导体存储器件减少通过数据总线传送的数据的高频噪声，从而数据的电压裕度提高，诸如电容器等无源器件的成本降低，并且该过程用于安装无源器件简化了。

6. 发明授权

US07239216B2 Semiconductor memory device with data bus scheme for reducing high frequency noise 有权
标题翻译：具有数据总线方案的半导体存储器件，用于降低高频噪声
公开(公告)号：US07239216B2
公开(公告)日：2007-07-03
申请号：US10424923
申请日：2003-04-29
申请人： Myun-Joo Park , Jae-Jun Lee
发明人： Myun-Joo Park , Jae-Jun Lee
IPC分类号： H01P5/12
CPC分类号： H05K1/0216 , G11C7/1006 , H05K1/0237 , H05K1/14 , H05K2201/044 , H05K2201/09727 , H05K2201/09781
摘要： A semiconductor memory device includes memory modules which have memories and a data bus which transfers data to the memory modules, in which the data bus comprises a low frequency band data pass unit which removes the high frequency component of the data and sends the data to the memory modules. The low frequency band data pass unit comprises a plurality of stubs which are connected to the data bus in parallel and are formed as printed circuit board (PCB) patterns. The low frequency band data pass unit comprises a plurality of plates that are connected to the data bus in parallel and are formed as PCB patterns. The low frequency band data pass unit has a shape in which parts having a wide width and parts having a narrow width are alternately connected. Therefore, without adding a separate passive device, the semiconductor memory device reduces the high frequency noise of data transferred through a data bus such that the voltage margin of the data improves, the cost for passive devices such as capacitors, is reduced, and the process for attaching the passive devices is simplified.
摘要翻译：半导体存储器件包括具有存储器的存储器模块和将数据传送到存储器模块的数据总线，其中数据总线包括低频带数据传递单元，该单元去除数据的高频分量并将数据发送到内存模块低频带数据传送单元包括并联连接到数据总线并形成为印刷电路板（PCB）图案的多个短截线。低频带数据传送单元包括并联连接到数据总线并形成为PCB图案的多个板。低频带数据传送单元具有宽度宽的部分和宽度窄的部分交替连接的形状。因此，在不添加单独的无源器件的情况下，半导体存储器件减少通过数据总线传送的数据的高频噪声，从而数据的电压裕度提高，诸如电容器等无源器件的成本降低，并且该过程用于安装无源器件简化了。

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