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1. 发明授权

US07940578B2 Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods 有权
标题翻译：具有共享单个高电压电平移位器的行解码器的闪存器件，包括其的系统以及相关联的方法
公开(公告)号：US07940578B2
公开(公告)日：2011-05-10
申请号：US12320003
申请日：2009-01-14
申请人： Myoung-gon Kang , Yeong-taek Lee , Ki-tae Park , Doo-gon Kim
发明人： Myoung-gon Kang , Yeong-taek Lee , Ki-tae Park , Doo-gon Kim
IPC分类号： G11C5/14
CPC分类号： G11C16/3418 , G11C7/02 , G11C8/10 , G11C16/0483 , G11C16/3427 , G11C17/16 , G11C29/52
摘要： A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.
摘要翻译：闪速存储器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块和第二存储单元阵列块的行解码器。行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

2. 发明申请

US20090185422A1 Flash memory device having row decoders sharing single high voltage level shifter, system including the same, and associated methods 有权
标题翻译：具有共享单个高电压电平移位器的行解码器的闪存器件，包括其的系统以及相关联的方法
公开(公告)号：US20090185422A1
公开(公告)日：2009-07-23
申请号：US12320003
申请日：2009-01-14
申请人： Myoung-gon Kang , Yeong-taek Lee , Ki-tae Park , Doo-gon Kim
发明人： Myoung-gon Kang , Yeong-taek Lee , Ki-tae Park , Doo-gon Kim
IPC分类号： G11C16/04 , G11C7/00 , G11C17/16 , G11C16/06
CPC分类号： G11C16/3418 , G11C7/02 , G11C8/10 , G11C16/0483 , G11C16/3427 , G11C17/16 , G11C29/52
摘要： A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.
摘要翻译：闪存器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块的行解码器和第二存储单元阵列块。存储单元阵列块。行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

3. 发明申请

US20080310230A1 Flash Memory Devices Having Three Dimensional Stack Structures and Methods of Driving Same 有权
标题翻译：具有三维堆叠结构的闪存器件及其驱动方法相同
公开(公告)号：US20080310230A1
公开(公告)日：2008-12-18
申请号：US12136933
申请日：2008-06-11
申请人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
发明人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/3418
摘要： Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.
摘要翻译：提供闪存器件，其包括垂直堆叠的多个层。多个层中的每一个包括多个存储单元。行解码器电耦合到多个层并且被配置为向多个层提供字线电压。提供在多个层中的至少两层中的存储单元属于相同的存储块，并且与多个层中的至少两个层中的存储单元相关联的字线电耦合。

4. 发明授权

US07911835B2 Programming and reading five bits of data in two non-volatile memory cells 失效
标题翻译：在两个非易失性存储单元中编程和读取五位数据
公开(公告)号：US07911835B2
公开(公告)日：2011-03-22
申请号：US11859465
申请日：2007-09-21
申请人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
发明人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628
摘要： Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. Programming includes first, second and third data bit program operations. In the first and second data bit program operation, the first and second non-volatile memory cells are programmed with the first or second threshold voltage level in order to store first and second bits of data. In the third data bit program operation, the first non-volatile memory cell is programmed with the third or fourth threshold voltage level according to the first and second bits of the data in order to store a third bit of the data. Fourth and fifth data bit program operations also may be provided.
摘要翻译：非易失性存储器件和非易失性存储器件的编程方法使用六个阈值电压电平。也可以从非易失性存储器件读取数据。非易失性存储器件包括第一非易失性存储器单元和第二非易失性存储器单元，其中每一个都可以用顺序增加的第一至第六阈值电压电平进行编程。编程包括第一，第二和第三数据位程序操作。在第一和第二数据位编程操作中，第一和第二非易失性存储单元用第一或第二阈值电压电平进行编程，以便存储第一和第二位数据。在第三数据比特编程操作中，根据数据的第一和第二比特，第一非易失性存储单元用第三或第四阈值电压电平进行编程，以便存储数据的第三位。也可以提供第四和第五数据位程序操作。

5. 发明申请

US20080084740A1 PROGRAMMING AND READING FIVE BITS OF DATA IN TWO NON-VOLATILE MEMORY CELLS 失效
标题翻译：在两个非易失性记忆细胞中编程和读取数据的五个位
公开(公告)号：US20080084740A1
公开(公告)日：2008-04-10
申请号：US11859465
申请日：2007-09-21
申请人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
发明人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628
摘要： Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. Programming includes first, second and third data bit program operations. In the first and second data bit program operation, the first and second non-volatile memory cells are programmed with the first or second threshold voltage level in order to store first and second bits of data. In the third data bit program operation, the first non-volatile memory cell is programmed with the third or fourth threshold voltage level according to the first and second bits of the data in order to store a third bit of the data. Fourth and fifth data bit program operations also may be provided.
摘要翻译：非易失性存储器件和非易失性存储器件的编程方法使用六个阈值电压电平。也可以从非易失性存储器件读取数据。非易失性存储器件包括第一非易失性存储器单元和第二非易失性存储器单元，其中每一个都可以用顺序增加的第一至第六阈值电压电平进行编程。编程包括第一，第二和第三数据位程序操作。在第一和第二数据位编程操作中，第一和第二非易失性存储单元用第一或第二阈值电压电平进行编程，以便存储第一和第二位数据。在第三数据比特编程操作中，根据数据的第一和第二比特，第一非易失性存储单元用第三或第四阈值电压电平进行编程，以便存储数据的第三位。也可以提供第四和第五数据位程序操作。

6. 发明授权

US07843733B2 Flash memory devices having three dimensional stack structures and methods of driving same 有权
标题翻译：具有三维堆栈结构的闪存器件及其驱动方法
公开(公告)号：US07843733B2
公开(公告)日：2010-11-30
申请号：US12136933
申请日：2008-06-11
申请人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
发明人： Doo-gon Kim , Ki-tae Park , Yeong-taek Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/3418
摘要： Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.
摘要翻译：提供闪存器件，其包括垂直堆叠的多个层。多个层中的每一个包括多个存储单元。行解码器电耦合到多个层并且被配置为向多个层提供字线电压。提供在多个层中的至少两层中的存储单元属于相同的存储块，并且与多个层中的至少两个层中的存储单元相关联的字线电耦合。

7. 发明授权

US08767450B2 Memory controllers to refresh memory sectors in response to writing signals and memory systems including the same 有权
标题翻译：存储器控制器用于刷新内存扇区以响应写入信号和包括其的存储器系统
公开(公告)号：US08767450B2
公开(公告)日：2014-07-01
申请号：US12662949
申请日：2010-05-13
申请人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-yon Lee , Dae-won Ha
发明人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-yon Lee , Dae-won Ha
IPC分类号： G11C11/00
CPC分类号： G11C16/3431 , G11C11/005 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1616
摘要： A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.
摘要翻译：存储器系统包括具有多个存储器扇区的存储单元阵列。每个存储器扇区包括多个存储单元。存储器系统还包括配置成响应于写入信号将数据写入存储单元阵列的控制器。控制器还被配置为在每次提供写入信号时刷新多个存储器扇区中的存储器扇区。当N（N是正整数）存储单元被编程时，编程电流小于或等于大约0.75mA * N。

8. 发明申请

US20100246247A1 Phase-change random access memories, memory devices, memory systems, methods of operating and methods of manufacturing the same 有权
标题翻译：相变随机存取存储器，存储器件，存储器系统，操作方法及其制造方法
公开(公告)号：US20100246247A1
公开(公告)日：2010-09-30
申请号：US12662949
申请日：2010-05-13
申请人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-von Lee , Dae-won Ha
发明人： Doo-gon Kim , Hui-kwon Seo , Cheol-kyu Kim , Sei-jin Kim , Yoon-ho Khang , Han-gu Sohn , Tae-von Lee , Dae-won Ha
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C16/3431 , G11C11/005 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1616
摘要： A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N.
摘要翻译：存储器系统包括具有多个存储器扇区的存储单元阵列。每个存储器扇区包括多个存储单元。存储器系统还包括配置成响应于写入信号将数据写入存储单元阵列的控制器。控制器还被配置为在每次提供写入信号时刷新多个存储器扇区中的存储器扇区。当N（N是正整数）存储单元被编程时，编程电流小于或等于大约0.75mA * N。

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