专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10032431B2 Mobile computing device technology and systems and methods utilizing the same 有权
公开(公告)号：US10032431B2
公开(公告)日：2018-07-24
申请号：US14768141
申请日：2014-03-13
申请人： Myles Wilde , Matthew J. Adiletta , William R. Wheeler , Michael F. Fallon , Thomas M. Garrison , Aaron Gorius , Chengda Yang
发明人： Myles Wilde , Matthew J. Adiletta , William R. Wheeler , Michael F. Fallon , Thomas M. Garrison , Aaron Gorius , Chengda Yang
IPC分类号： G09G5/00 , H04L29/06 , G06F13/38 , H04N19/423 , H04N19/44 , G06T1/60 , H04N5/38 , H04W4/18 , H04W4/21 , H04W4/80 , H04W76/14
摘要： Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.

2. 发明申请

US20090024804A1 MEMORY CONTROLLERS FOR PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS 有权
标题翻译：具有多个可编程单元的处理器的存储器控制器
公开(公告)号：US20090024804A1
公开(公告)日：2009-01-22
申请号：US12207476
申请日：2008-09-09
申请人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
发明人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G06F12/10
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

3. 发明授权

US07107201B2 Simulating a logic design 有权
标题翻译：模拟逻辑设计
公开(公告)号：US07107201B2
公开(公告)日：2006-09-12
申请号：US09941952
申请日：2001-08-29
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F17/50 , G06F9/455 , G06F9/44
CPC分类号： G06F17/5022
摘要： Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for the combinatorial logic and the state logic using the separate graphic elements, generating computer code that simulates operation of portions of the logic design, the computer code being generated based on the clock domains, and associating the computer code with graphic elements that correspond to the portions of the logic design.
摘要翻译：模拟具有组合逻辑和状态逻辑的逻辑设计包括使用分离的图形元素表示组合逻辑和状态逻辑，识别用于组合逻辑的时钟域和使用分离的图形元素的状态逻辑，生成计算机代码，其模拟部分的操作逻辑设计，基于时钟域产生的计算机代码，以及将计算机代码与对应于逻辑设计的部分的图形元素相关联。

4. 发明授权

US07093224B2 Model-based logic design 有权
公开(公告)号：US07093224B2
公开(公告)日：2006-08-15
申请号：US09941158
申请日：2001-08-28
申请人： William R. Wheeler , Matthew J. Adiletta , Christopher Clark , Timothy J. Fennel
发明人： William R. Wheeler , Matthew J. Adiletta , Christopher Clark , Timothy J. Fennel
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.

5. 发明授权

US07073156B2 Gate estimation process and method 失效
标题翻译：门估计过程和方法
公开(公告)号：US07073156B2
公开(公告)日：2006-07-04
申请号：US09941519
申请日：2001-08-29
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5045
摘要： A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design environment is monitored to detect the addition of a circuitry component to the circuit and a component design parameter file that specifies at least one design parameter for that added circuitry component is accessed. The circuit design parameter file is updated based on the design parameter(s) included in the component design parameter file. The circuit designer is provided with feedback concerning the physical characteristic of the circuit being designed.
摘要翻译：为由电路设计者设计的电路维护电路设计参数文件。该电路设计参数文件指定电路的物理特性。监视设计环境以检测电路组件到电路的添加，并且访问指定所添加的电路组件的至少一个设计参数的组件设计参数文件。电路设计参数文件根据组件设计参数文件中包含的设计参数进行更新。电路设计人员提供有关正在设计的电路的物理特性的反馈。

6. 发明授权

US06983350B1 SDRAM controller for parallel processor architecture 失效
标题翻译：用于并行处理器架构的SDRAM控制器
公开(公告)号：US06983350B1
公开(公告)日：2006-01-03
申请号：US09387109
申请日：1999-08-31
申请人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
发明人： William R. Wheeler , Bradley Burres , Matthew J. Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用引用是读取引用或写入引用。

7. 发明授权

US06721925B2 Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture 失效
标题翻译：采用智能逻辑模型来实现简洁的逻辑表示，以便设计描述清晰，并能快速设计
公开(公告)号：US06721925B2
公开(公告)日：2004-04-13
申请号：US10025193
申请日：2001-12-18
申请人： William R. Wheeler , Timothy J. Fennell , Matthew J. Adiletta
发明人： William R. Wheeler , Timothy J. Fennell , Matthew J. Adiletta
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
摘要翻译：代表逻辑设备通常包括创建逻辑设备的模型，其中模型表示逻辑设备的变体的集合。可以在逻辑设计中使用该模型的表示，并且可以基于对表示形成的连接来自动选择逻辑设备的特定变体。可以自动检测连接错误，并且当检测到连接错误时可以自动显示第一指示。当修正连接错误时，可以自动显示与第一指示不同的第二指示。

8. 发明申请

US20090307469A1 REGISTER SET USED IN MULTITHREADED PARALLEL PROCESSOR ARCHITECTURE 有权
标题翻译：多用途平行处理器结构中使用的寄存器
公开(公告)号：US20090307469A1
公开(公告)日：2009-12-10
申请号：US12477287
申请日：2009-06-03
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/00 , G06F12/00
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
摘要翻译：描述了基于并行硬件的多线程处理器。处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。处理器维护执行线程。执行线程访问组织成每个线程相对可寻址的多个相对可寻址的寄存器窗口的寄存器集。

9. 发明授权

US06983427B2 Generating a logic design 失效
公开(公告)号：US06983427B2
公开(公告)日：2006-01-03
申请号：US09942102
申请日：2001-08-29
申请人： William R. Wheeler , Matthew J. Adiletta
发明人： William R. Wheeler , Matthew J. Adiletta
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.

10. 发明授权

US06668311B2 Method for memory allocation and management using push/pop apparatus 有权
公开(公告)号：US06668311B2
公开(公告)日：2003-12-23
申请号：US09919058
申请日：2001-07-30
申请人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
发明人： Donald F. Hooper , Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式