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1. 发明申请

US20090150706A1 WRAPPER CIRCUIT FOR GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开
标题翻译：用于全球异地同步同步系统的封装电路及其操作方法
公开(公告)号：US20090150706A1
公开(公告)日：2009-06-11
申请号：US12186114
申请日：2008-08-05
申请人： Myeong-Hoon OH , Seong-Woon Kim , Myung-Joon Kim , Sung-Nam Kim
发明人： Myeong-Hoon OH , Seong-Woon Kim , Myung-Joon Kim , Sung-Nam Kim
IPC分类号： G06F1/12 , H04L7/00
CPC分类号： G06F1/08 , G06F1/3203
摘要： Provided are a high-performance wrapper circuit for a globally asynchronous locally synchronous (GALS) system and a synchronization method using the same, which are capable of solving a synchronization problem caused when data are transmitted between locally synchronous modules employing different clocks, and a method for operating the wrapper circuit. The GALS system includes a clock generator for supplying an operation clock to a locally synchronous module, a sender port for transmitting data to the outside according to a data transmission request signal output from the locally synchronous module, and generating a first clock stop signal for stopping an operation of the clock generator, and a receiver port for receiving data from the outside, and generating a second clock stop signal for stopping the operation of the clock generator. The sender port generates the first clock stop signal to the clock generator when a next data transmission request signal is received before completing a data transmission performed by a previous data transmission request signal output from the locally synchronous module.
摘要翻译：提供了一种用于全球异步本地同步（GALS）系统的高性能封装电路和使用该高性能封装电路的同步方法，其能够解决当采用不同时钟的本地同步模块之间传输数据时引起的同步问题，以及方法用于操作包装电路。 GALS系统包括用于向本地同步模块提供操作时钟的时钟发生器，用于根据从本地同步模块输出的数据发送请求信号向外部发送数据的发送器端口，以及生成用于停止的第一时钟停止信号时钟发生器的操作和用于从外部接收数据的接收器端口，以及产生用于停止时钟发生器的操作的第二时钟停止信号。当在完成由本地同步模块输出的先前数据传输请求信号执行的数据传输之前接收到下一个数据传输请求信号时，发送器端口产生到时钟发生器的第一个时钟停止信号。

2. 发明申请

US20120166170A1 DELAY CIRCUIT, AND DEVICE AND METHOD FOR SIMULATING ASYNCHRONOUS CIRCUIT IN FPGA USING DELAY CIRCUIT 审中-公开
标题翻译：延迟电路，以及使用延迟电路在FPGA中仿真异步电路的器件和方法
公开(公告)号：US20120166170A1
公开(公告)日：2012-06-28
申请号：US13334814
申请日：2011-12-22
申请人： Chi-Hoon Shin , Sung-Nam Kim , Myeong-Hoon Oh , Seong-Woon Kim , Jae-Woo Sim
发明人： Chi-Hoon Shin , Sung-Nam Kim , Myeong-Hoon Oh , Seong-Woon Kim , Jae-Woo Sim
IPC分类号： G06F17/50 , H03L7/00
CPC分类号： G06F17/5027 , G06F17/5059
摘要： Disclosed herein is an apparatus for simulating an asynchronous circuit in an FPGA. The apparatus includes a plurality of function execution units, a plurality of delay circuits, and a control unit. The function execution units are set for respective unit functions included in the asynchronous circuit, and are configured to perform the unit functions. The delay circuits are provided for the respective function execution units using a look-up table in the FPGA, and are configured to output delayed input signals by delaying input signals by respective preset delay times. The control unit transmits the input signals to the delay circuits and the function execution units, and receives the delayed input signals from the respective delay circuits.
摘要翻译：这里公开了一种用于在FPGA中模拟异步电路的装置。该装置包括多个功能执行单元，多个延迟电路和控制单元。功能执行单元被设置为包括在异步电路中的各个单元功能，并且被配置为执行单元功能。使用FPGA中的查找表为各个功能执行单元提供延迟电路，并且被配置为通过相应的预设延迟时间延迟输入信号来输出延迟的输入信号。控制单元将输入信号发送到延迟电路和功能执行单元，并且从各个延迟电路接收延迟的输入信号。

3. 发明授权

US08705592B2 Data transmission apparatus, data reception apparatus, and data transmission method 有权
标题翻译：数据发送装置，数据接收装置和数据发送方法
公开(公告)号：US08705592B2
公开(公告)日：2014-04-22
申请号：US13554327
申请日：2012-07-20
申请人： Myeong-Hoon Oh , Chi-Hoon Shin , Sung-Nam Kim , Seong-Woon Kim
发明人： Myeong-Hoon Oh , Chi-Hoon Shin , Sung-Nam Kim , Seong-Woon Kim
IPC分类号： H04L25/00 , H04B3/00 , G01R31/08
CPC分类号： G06F17/5059
摘要： Disclosed herein are a data transmission apparatus, a data reception apparatus, and a data transmission method. The data transmission apparatus, the data reception apparatus, and the data transmission method are capable of simplifying the circuit structure of a decoder because an assumption of the time related to a request signal and a data signal is not necessary and an additional logic for generating a clock signal for the decoder is not necessary by using a Finite State Machine (FSM) logic without storing a state via a delay device.
摘要翻译：这里公开了数据发送装置，数据接收装置和数据发送方法。数据发送装置，数据接收装置和数据发送方法能够简化解码器的电路结构，因为与请求信号和数据信号相关的时间的假定不是必需的，并且用于生成通过使用有限状态机（FSM）逻辑而不通过延迟器件存储状态，解码器的时钟信号不是必需的。

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