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1. 发明授权

US08026482B2 Charged particle beam apparatus and control method therefor 有权
标题翻译：带电粒子束装置及其控制方法
公开(公告)号：US08026482B2
公开(公告)日：2011-09-27
申请号：US12142284
申请日：2008-06-19
申请人： Muneyuki Fukuda , Hiromasa Yamanashi , Sayaka Tanimoto , Yasunari Souda , Osamu Nasu
发明人： Muneyuki Fukuda , Hiromasa Yamanashi , Sayaka Tanimoto , Yasunari Souda , Osamu Nasu
IPC分类号： G21K5/00 , G21K1/00
CPC分类号： H01J37/28 , H01J37/026 , H01J37/265 , H01J2237/24564
摘要： Potentials at a plurality of points on a diameter of a semiconductor wafer 13 are measured actually. Then, a potential distribution on the diameter is obtained by spline interpolation of potentials between the actually-measured points adjacent in the diameter direction. Thereafter, a two-dimensional interpolation function regarding a potential distribution in the semiconductor wafer 13 is obtained by spline interpolation of potentials between points adjacent in the circumferential direction around the center of the semiconductor wafer 13. Then, a potential at a observation point on the semiconductor wafer 13 is obtained by substituting the coordinate value of this observation point into the two-dimensional interpolation function. As a result, a potential distribution due to electrification of the wafer can be estimated accurately, and the retarding potential can be set to a suitable value.
摘要翻译：实际上测量半导体晶片13的直径上的多个点上的电位。然后，通过在直径方向上相邻的实测点之间的电位的样条插值来获得直径上的电位分布。此后，通过对在半导体晶片13的中心周围的圆周方向相邻的点之间的电位进行样条插补，获得关于半导体晶片13中的电位分布的二维内插函数。然后，在通过将该观察点的坐标值代入二维插值函数来获得半导体晶片13。结果，可以精确地估计由于晶片带电引起的电位分布，并且可以将延迟电位设置为适当的值。

2. 发明申请

US20090140143A1 CHARGED PARTICLE BEAM APPARATUS AND CONTROL METHOD THEREFOR 有权
标题翻译：充电颗粒光束装置及其控制方法
公开(公告)号：US20090140143A1
公开(公告)日：2009-06-04
申请号：US12142284
申请日：2008-06-19
申请人： Muneyuki FUKUDA , Hiromasa Yamanashi , Sayaka Tanimoto , Yasunari Souda , Osamu Nasu
发明人： Muneyuki FUKUDA , Hiromasa Yamanashi , Sayaka Tanimoto , Yasunari Souda , Osamu Nasu
IPC分类号： G21K5/00 , G21K1/00
CPC分类号： H01J37/28 , H01J37/026 , H01J37/265 , H01J2237/24564
摘要： Potentials at a plurality of points on a diameter of a semiconductor wafer 13 are measured actually. Then, a potential distribution on the diameter is obtained by spline interpolation of potentials between the actually-measured points adjacent in the diameter direction. Thereafter, a two-dimensional interpolation function regarding a potential distribution in the semiconductor wafer 13 is obtained by spline interpolation of potentials between points adjacent in the circumferential direction around the center of the semiconductor wafer 13. Then, a potential at a observation point on the semiconductor wafer 13 is obtained by substituting the coordinate value of this observation point into the two-dimensional interpolation function. As a result, a potential distribution due to electrification of the wafer can be estimated accurately, and the retarding potential can be set to a suitable value.
摘要翻译：实际上测量半导体晶片13的直径上的多个点上的电位。然后，通过在直径方向上相邻的实测点之间的电位的样条插值来获得直径上的电位分布。此后，通过对在半导体晶片13的中心周围的圆周方向相邻的点之间的电位进行样条插补，获得关于半导体晶片13中的电位分布的二维内插函数。然后，在通过将该观察点的坐标值代入二维插值函数来获得半导体晶片13。结果，可以精确地估计由于晶片带电引起的电位分布，并且可以将延迟电位设置为适当的值。

3. 发明授权

US08217351B2 Pattern inspection method and pattern inspection system 有权
标题翻译：图案检验方法和图案检验制度
公开(公告)号：US08217351B2
公开(公告)日：2012-07-10
申请号：US12858209
申请日：2010-08-17
申请人： Yasutaka Toyoda , Yasunari Souda , Yuji Takagi , Koji Arai
发明人： Yasutaka Toyoda , Yasunari Souda , Yuji Takagi , Koji Arai
IPC分类号： G06K9/46 , G01N23/00
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A pattern data examination method and system capable of accurately and speedily examining a circuit pattern without failing to extract pattern contour data are provided. While pattern comparison is ordinarily made by using a secondary electron image, a contour of a pattern element is extracted by using a backscattered electron image said to be suitable for observation and examination of a three dimensional configuration of a pattern element, and pattern inspection is executed by using the extracted contour of the pattern element. More specifically, pattern inspection is executed by comparing a contour of a pattern element with design data such as CAD data to measure a difference between the contour and the data, and by computing, for example, the size of the circuit pattern element from the contour of a pattern. From two or more backscattered electron images formed by detecting backscattered electrons at two or more different spatial positions, pattern contour data contained in the backscattered electron images may be obtained.
摘要翻译：提供了能够准确且快速地检查电路图案而不会提取图案轮廓数据的图形数据检查方法和系统。虽然通常使用二次电子图像进行图案比较，但是通过使用所述适合于观察和检查图案元素的三维构造的背散射电子图像来提取图案元素的轮廓，并且执行图案检查通过使用所提取的图案元素的轮廓。更具体地，通过将图案元素的轮廓与诸如CAD数据的设计数据进行比较来测量轮廓和数据之间的差异，并且例如通过计算来自轮廓的电路图案元素的尺寸来执行图案检查的模式。通过在两个或更多个不同的空间位置检测反向散射电子形成的两个或更多个背散射电子图像，可以获得包含在背散射电子图像中的图案轮廓数据。

4. 发明申请

US20090039261A1 Pattern Inspection Method and Pattern Inspection System 有权
标题翻译：模式检验方法和模式检验系统
公开(公告)号：US20090039261A1
公开(公告)日：2009-02-12
申请号：US12188096
申请日：2008-08-07
申请人： Yasutaka Toyoda , Yasunari Souda , Yuji Takagi , Koji Arai
发明人： Yasutaka Toyoda , Yasunari Souda , Yuji Takagi , Koji Arai
IPC分类号： G01N23/00
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A pattern data examination method and system capable of accurately and speedily examining a circuit pattern without failing to extract pattern contour data are provided. While pattern comparison is ordinarily made by using a secondary electron image, a contour of a pattern element is extracted by using a backscattered electron image said to be suitable for observation and examination of a three dimensional configuration of a pattern element, and pattern inspection is executed by using the extracted contour of the pattern element. More specifically, pattern inspection is executed by comparing a contour of a pattern element with design data such as CAD data to measure a difference between the contour and the data, and by computing, for example, the size of the circuit pattern element from the contour of a pattern. From two or more backscattered electron images formed by detecting backscattered electrons at two or more different spatial positions, pattern contour data contained in the backscattered electron images may be obtained.
摘要翻译：提供了能够准确且快速地检查电路图案而不会提取图案轮廓数据的图形数据检查方法和系统。虽然通常使用二次电子图像进行图案比较，但是通过使用所述适合于观察和检查图案元素的三维构造的背散射电子图像来提取图案元素的轮廓，并且执行图案检查通过使用所提取的图案元素的轮廓。更具体地，通过将图案元素的轮廓与诸如CAD数据的设计数据进行比较来测量轮廓和数据之间的差异，并且例如通过计算来自轮廓的电路图案元素的尺寸来执行图案检查的模式。通过在两个或更多个不同的空间位置检测反向散射电子形成的两个或更多个背散射电子图像，可以获得包含在背散射电子图像中的图案轮廓数据。

5. 发明授权

US07067830B2 Multi-electron beam exposure method and apparatus 有权
标题翻译：多电子束曝光方法及装置
公开(公告)号：US07067830B2
公开(公告)日：2006-06-27
申请号：US10629623
申请日：2003-07-30
申请人： Haruo Yoda , Yasunari Souda , Hiroya Ohta , Yoshikiyo Yui , Shinichi Hashimoto
发明人： Haruo Yoda , Yasunari Souda , Hiroya Ohta , Yoshikiyo Yui , Shinichi Hashimoto
IPC分类号： H01J37/08
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3177 , H01J2237/31764 , H01J2237/31767
摘要： The dimension of the main field as a unit region for exposure is set to an integral submultiple of the arrangement pitch of the LSI to be exposed, by the control computer 62, and the exposure data stored in the form associated with electron beams from a data generation circuit 64 is limited to one-chip data alone in units of a stripe. This data is repeatedly read out to write the stripe. Further, a storage circuit 66 is provided to store the exposure data by means of a double buffer memory unit for each electron beam. While LSI is written according to one of the buffers, the next exposure stripe data is prepared on the other buffer, thereby bringing about a substantial reduction in the required speed of the exposure data generation circuit.
摘要翻译：通过控制计算机62将作为曝光的单位区域的主场的尺寸设定为要暴露的LSI的排列间距的整数倍，并且以与来自数据的电子束相关联的形式存储的曝光数据发生电路64仅以条形为单位限于单芯片数据。该数据被重复读出以写入条带。此外，存储电路66用于通过用于每个电子束的双缓冲存储器单元来存储曝光数据。当根据缓冲器中的一个写入LSI时，在另一个缓冲器上准备下一个曝光条带数据，从而显着降低曝光数据产生电路的所需速度。

6. 发明授权

US07126140B2 Multi-electron beam exposure method and apparatus 有权
标题翻译：多电子束曝光方法及装置
公开(公告)号：US07126140B2
公开(公告)日：2006-10-24
申请号：US11213750
申请日：2005-08-30
申请人： Haruo Yoda , Yasunari Souda , Hiroya Ohta , Yoshikiyo Yui , Shinichi Hashimoto
发明人： Haruo Yoda , Yasunari Souda , Hiroya Ohta , Yoshikiyo Yui , Shinichi Hashimoto
IPC分类号： H01J37/08
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3177 , H01J2237/31764 , H01J2237/31767
摘要： A multi-electron beam exposure method and apparatus, wherein electron beams are applied to a sample surface mounted on a traveling sample stage to perform repeated exposure of chip patterns. An exposure region of the sample surface is partitioned into multiple stripe regions having a width in an x-axis direction, and each of the multiple stripe regions is further partitioned into multiple main fields having a width in a y-axis direction. At least one of the widths of the main fields in the x- and y-axis directions is set to a value, and exposure pattern data for one chip based on the partitioned main fields is stored as a unit. The stored exposure pattern data is readout a number of times corresponding to the number of chips repeatedly, and each electron beam provides repeated exposure of same regions of the chips.
摘要翻译：一种多电子束曝光方法和装置，其中将电子束施加到安装在行进样品台上的样品表面，以进行芯片图案的重复曝光。将样品表面的曝光区域划分为具有x轴方向宽度的多个条纹区域，并且将多个条纹区域中的每一个进一步划分为具有y轴方向宽度的多个主场。将x轴方向和y轴方向上的主场的宽度中的至少一个设定为一个值，并且将基于分割的主场的一个芯片的曝光图案数据作为一个单元存储。存储的曝光图案数据被重复读出与芯片数量相对应的次数，并且每个电子束提供芯片的相同区域的重复曝光。

7. 发明申请

US20060017021A1 Multi-electron beam exposure method and apparatus 有权
公开(公告)号：US20060017021A1
公开(公告)日：2006-01-26
申请号：US11213750
申请日：2005-08-30
申请人： Haruo Yoda , Yasunari Souda , Hiroya Ohta , Yoshikiyo Yui , Shinichi Hashimoto
发明人： Haruo Yoda , Yasunari Souda , Hiroya Ohta , Yoshikiyo Yui , Shinichi Hashimoto
IPC分类号： G21K5/10
CPC分类号： B82Y10/00 , B82Y40/00 , H01J37/3177 , H01J2237/31764 , H01J2237/31767
摘要： A multi-electron beam exposure method and apparatus, wherein electron beams are applied to a sample surface mounted on a traveling sample stage to perform repeated exposure of chip patterns. An exposure region of the sample surface is partitioned into multiple stripe regions having a width in an x-axis direction, and each of the multiple stripe regions is further partitioned into multiple main fields having a width in a y-axis direction. At least one of the widths of the main fields in the x- and y-axis directions is set to a value, and exposure pattern data for one chip based on the partitioned main fields is stored as a unit. The stored exposure pattern data is readout a number of times corresponding to the number of chips repeatedly, and each electron beam provides repeated exposure of same regions of the chips.

8. 发明申请

US20100310180A1 Pattern Inspection Method and Pattern Inspection System 有权
标题翻译：模式检验方法和模式检验系统
公开(公告)号：US20100310180A1
公开(公告)日：2010-12-09
申请号：US12858209
申请日：2010-08-17
申请人： Yasutaka TOYODA , Yasunari Souda , Yuji Takagi , Koji Arai
发明人： Yasutaka TOYODA , Yasunari Souda , Yuji Takagi , Koji Arai
IPC分类号： G06K9/46
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A pattern data examination method and system capable of accurately and speedily examining a circuit pattern without failing to extract pattern contour data are provided. While pattern comparison is ordinarily made by using a secondary electron image, a contour of a pattern element is extracted by using a backscattered electron image said to be suitable for observation and examination of a three dimensional configuration of a pattern element, and pattern inspection is executed by using the extracted contour of the pattern element. More specifically, pattern inspection is executed by comparing a contour of a pattern element with design data such as CAD data to measure a difference between the contour and the data, and by computing, for example, the size of the circuit pattern element from the contour of a pattern. From two or more backscattered electron images formed by detecting backscattered electrons at two or more different spatial positions, pattern contour data contained in the backscattered electron images may be obtained.
摘要翻译：提供了能够准确且快速地检查电路图案而不会提取图案轮廓数据的图形数据检查方法和系统。虽然通常使用二次电子图像进行图案比较，但是通过使用所述适合于观察和检查图案元素的三维构造的背散射电子图像来提取图案元素的轮廓，并且执行图案检查通过使用所提取的图案元素的轮廓。更具体地，通过将图案元素的轮廓与诸如CAD数据的设计数据进行比较来测量轮廓和数据之间的差异，并且例如通过计算来自轮廓的电路图案元素的尺寸来执行图案检查的模式。通过在两个或更多个不同的空间位置检测反向散射电子形成的两个或更多个背散射电子图像，可以获得包含在背散射电子图像中的图案轮廓数据。

9. 发明授权

US07786437B2 Pattern inspection method and pattern inspection system 有权
标题翻译：图案检验方法和图案检验制度
公开(公告)号：US07786437B2
公开(公告)日：2010-08-31
申请号：US12188096
申请日：2008-08-07
申请人： Yasutaka Toyoda , Yasunari Souda , Yuji Takagi , Koji Arai
发明人： Yasutaka Toyoda , Yasunari Souda , Yuji Takagi , Koji Arai
IPC分类号： G01N23/00 , G06K9/00
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A pattern data examination method and system capable of accurately and speedily examining a circuit pattern without failing to extract pattern contour data are provided. While pattern comparison is ordinarily made by using a secondary electron image, a contour of a pattern element is extracted by using a backscattered electron image said to be suitable for observation and examination of a three dimensional configuration of a pattern element, and pattern inspection is executed by using the extracted contour of the pattern element. More specifically, pattern inspection is executed by comparing a contour of a pattern element with design data such as CAD data to measure a difference between the contour and the data, and by computing, for example, the size of the circuit pattern element from the contour of a pattern. From two or more backscattered electron images formed by detecting backscattered electrons at two or more different spatial positions, pattern contour data contained in the backscattered electron images may be obtained.
摘要翻译：提供了能够准确且快速地检查电路图案而不会提取图案轮廓数据的图形数据检查方法和系统。虽然通常使用二次电子图像进行图案比较，但是通过使用所述适合于观察和检查图案元素的三维构造的背散射电子图像来提取图案元素的轮廓，并且执行图案检查通过使用所提取的图案元素的轮廓。更具体地，通过将图案元素的轮廓与诸如CAD数据的设计数据进行比较来测量轮廓和数据之间的差异，并且例如通过计算来自轮廓的电路图案元素的尺寸来执行图案检查的模式。通过在两个或更多个不同的空间位置检测反向散射电子形成的两个或更多个背散射电子图像，可以获得包含在背散射电子图像中的图案轮廓数据。

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