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1. 发明授权

US08477855B2 Signal transmission system and semiconductor integrated circuit device 有权
标题翻译：信号传输系统和半导体集成电路器件
公开(公告)号：US08477855B2
公开(公告)日：2013-07-02
申请号：US12162687
申请日：2007-01-17
申请人： Muneo Fukaishi , Yoshihiro Nakagawa , Tadahiro Kuroda
发明人： Muneo Fukaishi , Yoshihiro Nakagawa , Tadahiro Kuroda
IPC分类号： H04L7/02 , H04B5/00
CPC分类号： H04B5/02 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.
摘要翻译：公开了一种半导体集成电路器件，其包括感应耦合到发送线圈的发送电路和接收线圈。发送电路不是在数据转换时通过发送线圈提供电流而是在数据传输中使用的时钟的每个上升沿或下降沿发送数据。在时钟的每个上升沿或下降沿，接收电路捕获由于流过发送线圈的电流而在接收线圈中感应的电压，再现发送的数据并输出再现的数据。

2. 发明申请

US20090322383A1 SEMICONDUCTOR DEVICE, SIGNAL TRANSMITTER, AND SIGNAL TRANSMISSION METHOD 审中-公开
标题翻译：半导体器件，信号发射器和信号传输方法
公开(公告)号：US20090322383A1
公开(公告)日：2009-12-31
申请号：US12304397
申请日：2007-06-01
申请人： Muneo Fukaishi , Yoshihiro Nakagawa , Tadahiro Kuroda
发明人： Muneo Fukaishi , Yoshihiro Nakagawa , Tadahiro Kuroda
IPC分类号： H03K3/00
CPC分类号： H03K17/6872 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided with a plurality of semiconductor chips and at least one transmission coil (108) for transmitting signals by using inductor coupling between the semiconductor chips. A plurality of transmission coils are connected in series.
摘要翻译：半导体器件设置有多个半导体芯片和至少一个用于通过使用半导体芯片之间的电感耦合来发送信号的传输线圈（108）。多个传输线圈串联连接。

3. 发明申请

US20090196388A1 SIGNAL TRANSMISSION SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：信号传输系统和半导体集成电路设备
公开(公告)号：US20090196388A1
公开(公告)日：2009-08-06
申请号：US12162687
申请日：2007-01-17
申请人： Muneo Fukaishi , Yoshihiro Nakagawa , Tadahiro Kuroda
发明人： Muneo Fukaishi , Yoshihiro Nakagawa , Tadahiro Kuroda
IPC分类号： H04L7/02 , H04B5/00
CPC分类号： H04B5/02 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.
摘要翻译：公开了一种半导体集成电路器件，其包括感应耦合到发送线圈的发送电路和接收线圈。发送电路不是在数据转换时通过发送线圈提供电流而是在数据传输中使用的时钟的每个上升沿或下降沿发送数据。在时钟的每个上升沿或下降沿，接收电路捕获由于流过发送线圈的电流而在接收线圈中感应的电压，再现发送的数据并输出再现的数据。

4. 发明授权

US09979441B2 Inductive relayed coupling circuit between substrates 有权
公开(公告)号：US09979441B2
公开(公告)日：2018-05-22
申请号：US12737025
申请日：2009-06-01
申请人： Tadahiro Kuroda
发明人： Tadahiro Kuroda
IPC分类号： H04B5/00 , H04B5/02 , H02J50/10 , H01L23/48 , H01L23/522 , H01L23/00 , H01L25/065
CPC分类号： H04B5/02 , H01L23/48 , H01L23/5227 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2223/6677 , H01L2224/05599 , H01L2224/32145 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/4911 , H01L2224/73265 , H01L2224/85399 , H01L2225/06527 , H01L2225/06555 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H02J50/10 , H04B5/0093 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： An electronic circuit carries out communication by inductive coupling between chips which are stacked and mounted. The electronic circuit relays an inter-chip communication signal by a repeater which receives a signal from a transmitter to recognize a transmission source and a receiving destination, and relays a received signal when the repeater itself exists between the transmission source and the receiving destination, and does not relay the received signal when the repeater itself does not exist between the transmission source and the receiving destination. Accordingly, data can be transferred at high speed up to a chip farther than the dimensions of a coil through communications by inductive coupling between the stacked and mounted chips.

5. 发明授权

US09419684B2 Inter-module communication apparatus 有权
标题翻译：模块间通信装置
公开(公告)号：US09419684B2
公开(公告)日：2016-08-16
申请号：US14000350
申请日：2012-02-14
申请人： Tadahiro Kuroda , Hiroki Ishikuro
发明人： Tadahiro Kuroda , Hiroki Ishikuro
IPC分类号： H04B5/00
CPC分类号： H04B5/0018 , H04B5/0012 , H04B5/0075 , H04B2203/5483
摘要： The invention relates to an inter-module communication apparatus where the reflection is reduced so that the communication channel can provide high speed and broadband as compared to inductive coupling. When modules having a signal line terminated with a terminating member and a feedback signal line are layered on top of each other so that the signal lines are coupled to each other and the return signal lines are coupled to each other using capacitive coupling and inductive coupling, the impedance of the terminating members is a coupling impedance that reflects the proximity effects in the coupling state between the modules.
摘要翻译：本发明涉及一种模块间通信装置，其中反射被减小，使得与电感耦合相比，通信信道可以提供高速和宽带。当具有以端接部件和反馈信号线端接的信号线的模块层叠在彼此的顶部上时，使得信号线彼此耦合，并且返回信号线使用电容耦合和电感耦合彼此耦合，端接构件的阻抗是反映模块之间耦合状态下的邻近效应的耦合阻抗。

6. 发明授权

US08872609B2 Inductor element and integrated circuit device 有权
标题翻译：电感元件和集成电路器件
公开(公告)号：US08872609B2
公开(公告)日：2014-10-28
申请号：US13203403
申请日：2010-02-19
申请人： Tadahiro Kuroda
发明人： Tadahiro Kuroda
IPC分类号： H01F27/32
CPC分类号： H01L23/5227 , H01F17/0006 , H01F2017/008 , H01L23/5225 , H01L2924/0002 , H01L2924/3011 , H04B5/0031 , H04B5/0081 , H01L2924/00
摘要： The invention relates to an inductor element and an integrated circuit device where the efficiency of use of wire materials is high and noise interference through capacitive/inductive coupling from peripheral wires is low.Coil elements 1, 2 are provided in at least two adjacent layer levels having main wires which run in different directions so that each coil element 1 (2) is connected to a coil element 2 (1) in a different layer level so as to form one coil, and shield wires 3, 4 are connected to a power 5 either above or below or to the left or right of said coil elements 1, 2.
摘要翻译：本发明涉及一种电感器元件和集成电路器件，其中线材的使用效率高，并且通过来自外围线的电容/电感耦合的噪声干扰低。线圈元件1,2设置在具有沿不同方向延伸的主线的至少两个相邻层级中，使得每个线圈元件1（2）以不同的层级连接到线圈元件2（1），以形成一个线圈和屏蔽线3,4连接到所述线圈元件1,2的左侧或右侧的电源5。

7. 发明申请

US20110133309A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110133309A1
公开(公告)日：2011-06-09
申请号：US13058423
申请日：2009-08-06
申请人： Tadahiro Kuroda
发明人： Tadahiro Kuroda
IPC分类号： H01L23/52 , H01L21/50
CPC分类号： H01L25/0657 , G11C5/02 , G11C5/06 , G11C29/88 , H01L25/18 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2924/01004 , H01L2924/01019 , H01L2924/14 , H01L2924/30107 , H01L2924/00014 , H01L2924/00012
摘要： The invention relates to a semiconductor device and a manufacturing method for the same, and makes the rejection rate of the product after chips are stacked and mounted sufficiently low, even when the chips are selected in a conventional, simple and inexpensive wafer test.A first device where a number of first semiconductor chips and a second semiconductor chip for controlling communication between the first semiconductor chips and the outside or communication between the first semiconductor chips are stacked and a second device having at least one third semiconductor chip that communicates with the second semiconductor chip are mounted on a substrate, wherein the third semiconductor chip functions to substitute a first semiconductor chip, there are at least the same number of third semiconductor chips as there are first semiconductor chips that do not operate normally, from among the first semiconductor chips within the first device, and the third semiconductor chips are stacked so as to substitute the functions of the first semiconductor chips that do not operate normally.
摘要翻译：本发明涉及一种半导体器件及其制造方法，并且即使当以常规，简单且廉价的晶片测试来选择芯片时，芯片堆叠并安装得足够低的产品的抑制率也将降低。第一装置，其中堆叠有多个第一半导体芯片和用于控制第一半导体芯片与外部之间的通信或第一半导体芯片之间的通信的第二半导体芯片，以及具有至少一个第三半导体芯片的第二装置，第二半导体芯片安装在基板上，其中第三半导体芯片用于替代第一半导体芯片，至少相同数量的第三半导体芯片与第一半导体芯片不同于第一半导体芯片的正常工作，第一半导体芯片第一器件内的芯片和第三半导体芯片被堆叠，以代替不正常工作的第一半导体芯片的功能。

8. 发明申请

US20080258744A1 Electronic Circuit Testing Apparatus 有权
标题翻译：电子电路测试仪器
公开(公告)号：US20080258744A1
公开(公告)日：2008-10-23
申请号：US11664262
申请日：2005-09-21
申请人： Tadahiro Kuroda , Daisuke Mizoguchi , Noriyuki Mirua
发明人： Tadahiro Kuroda , Daisuke Mizoguchi , Noriyuki Mirua
IPC分类号： G01R31/315
CPC分类号： G01R31/315 , G01R31/3025
摘要： The present invention has an object to provide an electronic circuit testing apparatus that is preferable for testing an electronic circuit which carries out communications between substrates based on inductive coupling and is capable of testing the electronic circuit without using test pads, wherein a probe 15 is caused to intervene in a communications channel composed by inductive coupling based on the first and second transmitter coils 21a, 21b; and the first and second receiver coils 23a, 23b, and an LSI is tested by a tester 11, buffers 12 and 13, and a Tx/Rx switch 14. Accordingly, it is not be necessary for that the electronic circuit testing apparatus is provided with a needle that touches pads and leads of the electronic circuit, and the service life there can be lengthened.
摘要翻译：本发明的目的是提供一种电子电路测试装置，其优选用于测试基于电感耦合在基板之间进行通信的电子电路，并且能够在不使用测试焊盘的情况下测试电子电路，其中引起探针15 介入基于第一和第二发射机线圈21a，21b的感应耦合组成的通信信道; 并且由测试器11，缓冲器12和13以及Tx / Rx开关14测试第一和第二接收器线圈23a，23b和LSI。因此，电子电路测试装置不需要设有接触电子电路的焊盘和引线的针，并且可以延长其使用寿命。

9. 发明授权

US6051442A CMOS integrated circuit device and its inspecting method and device 失效
标题翻译： CMOS集成电路器件及其检测方法及装置
公开(公告)号：US6051442A
公开(公告)日：2000-04-18
申请号：US831193
申请日：1997-04-02
申请人： Tadahiro Kuroda
发明人： Tadahiro Kuroda
IPC分类号： G01R31/26 , G01R31/28 , G01R31/30 , H01L21/66 , H01L21/8238 , H01L27/092 , H01L21/00
CPC分类号： G01R31/3004
摘要： The disclosed device and method can inspect the CMOS integrated circuit devices at high precision on the basis of the static current of the voltage supply connected thereto. A CMOS integrated circuit comprises: at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor; a first pad connected to a source of the P-channel MOS transistor; a second pad connected to a source of the N-channel MOS transistor; a third pad connected to an N-type substrate or an N-type well formed with the P-channel MOS transistor; and a fourth pad connected to a P-type substrate or a P-type well formed with the N-channel MOS transistor.
摘要翻译：所公开的装置和方法可以基于与其连接的电压源的静态电流以高精度检查CMOS集成电路装置。 CMOS集成电路包括：至少一个具有至少一个P沟道MOS晶体管和至少一个N沟道MOS晶体管的CMOS电路; 连接到所述P沟道MOS晶体管的源极的第一焊盘; 连接到所述N沟道MOS晶体管的源极的第二焊盘; 连接到N型衬底的第三焊盘或者与P沟道MOS晶体管形成的N型阱; 以及连接到P型衬底或与N沟道MOS晶体管形成的P型阱的第四焊盘。

10. 发明授权

US5742183A Level shift semiconductor device 失效
标题翻译：电平变换半导体器件
公开(公告)号：US5742183A
公开(公告)日：1998-04-21
申请号：US702924
申请日：1996-08-26
申请人： Tadahiro Kuroda
发明人： Tadahiro Kuroda
IPC分类号： H03K5/02 , H03K19/0185
CPC分类号： H03K19/018521
摘要： A level shift semiconductor device converts a signal level into another level between circuits connected to each other having different supply voltages. An input signal is supplied to the source of a first MOS transistor of a first-conductivity type (NMOS). The drain of the 1st NMOS transistor is connected to the input terminal of an inverter. An output signal is outputted via the output terminal of the inverter. The drain and gate of a first MOS transistor of a second-conductivity type (PMOS) are connected to the input and output terminals of the inverter, respectively. The gate and source of a second NMOS transistor are connected to the output terminal of the inverter and the gate of the 1st NMOS transistor, respectively. The gate and source of a second PMOS transistor are connected to the gate and source of the 2nd NMOS transistor. A first supply voltage is supplied to the drain of the 2nd PMOS transistor. And, a second supply voltage is supplied to the inverter, the source of the 1st PMOS transistor, and the drain of the 2nd NMOS transistor. The second voltage is larger in absolute value than the first voltage.
摘要翻译：电平移位半导体器件将信号电平转换为具有不同电源电压的彼此连接的电路之间的另一个电平。输入信号被提供给第一导电类型（NMOS）的第一MOS晶体管的源极。第一个NMOS晶体管的漏极连接到逆变器的输入端。输出信号通过变频器的输出端输出。第二导电类型（PMOS）的第一MOS晶体管的漏极和栅极分别连接到逆变器的输入和输出端子。第二NMOS晶体管的栅极和源极分别连接到反相器的输出端和第一NMOS晶体管的栅极。第二PMOS晶体管的栅极和源极连接到第二NMOS晶体管的栅极和源极。第一电源电压被提供给第二PMOS晶体管的漏极。并且，向逆变器，第一PMOS晶体管的源极和第二NMOS晶体管的漏极提供第二电源电压。第二电压的绝对值大于第一电压。

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