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1. 发明授权

US07281667B2 Method and structure for implementing secure multichip modules for encryption applications 失效
标题翻译：用于实施用于加密应用的安全多芯片模块的方法和结构
公开(公告)号：US07281667B2
公开(公告)日：2007-10-16
申请号：US10907761
申请日：2005-04-14
申请人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
发明人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
IPC分类号： G06K19/06
CPC分类号： G06K19/07381 , H01L23/04 , H01L23/055 , H01L23/10 , H01L23/576 , H01L25/0655 , H01L2224/16225 , H01L2224/16227 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/3011 , H05K1/0275 , H05K1/0306 , H05K1/144 , H05K2201/09263 , H05K2201/10151
摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
摘要翻译：防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。导电栅格结构被配置为检测穿透IC模块的尝试。

2. 发明授权

US07472836B2 Method and structure for implementing secure multichip modules for encryption applications 失效
标题翻译：用于实施用于加密应用的安全多芯片模块的方法和结构
公开(公告)号：US07472836B2
公开(公告)日：2009-01-06
申请号：US11768312
申请日：2007-06-26
申请人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D. Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
发明人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D. Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
IPC分类号： G06K19/05
CPC分类号： G06K19/07381 , H01L23/04 , H01L23/055 , H01L23/10 , H01L23/576 , H01L25/0655 , H01L2224/16225 , H01L2224/16227 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/3011 , H05K1/0275 , H05K1/0306 , H05K1/144 , H05K2201/09263 , H05K2201/10151
摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
摘要翻译：防干扰集成电路（IC）模块包括陶瓷芯片载体，附接到芯片载体的一个或多个集成电路芯片，以及附接到芯片载体的覆盖一个或多个集成电路芯片的盖结构。在芯片载体和盖结构中形成导电栅格结构，该导电结构具有沿x方向，y方向和z方向设置的多条曲折线。导电栅格结构被配置为检测穿透IC模块的尝试。

3. 发明申请

US20090145973A1 STRUCTURE FOR IMPLEMENTING SECURE MULTICHIP MODULES FOR ENCRYPTION APPLICATIONS 有权
标题翻译：用于实施加密应用的安全多模块模块的结构
公开(公告)号：US20090145973A1
公开(公告)日：2009-06-11
申请号：US12348364
申请日：2009-01-05
申请人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D. Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
发明人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D. Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
IPC分类号： G06K19/06
CPC分类号： G06K19/07381 , H01L23/04 , H01L23/055 , H01L23/10 , H01L23/576 , H01L25/0655 , H01L2224/16225 , H01L2224/16227 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/3011 , H05K1/0275 , H05K1/0306 , H05K1/144 , H05K2201/09263 , H05K2201/10151
摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
摘要翻译：防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。

4. 发明授权

US07806341B2 Structure for implementing secure multichip modules for encryption applications 有权
标题翻译：用于实现加密应用的安全多芯片模块的结构
公开(公告)号：US07806341B2
公开(公告)日：2010-10-05
申请号：US12348364
申请日：2009-01-05
申请人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D. Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
发明人： Mukta G. Farooq , Benjamin V. Fasano , Jason L. Frankel , Harvey C. Hamel , Suresh D. Kadakia , David C. Long , Frank L. Pompeo , Sudipta K. Ray
IPC分类号： G06K19/05
CPC分类号： G06K19/07381 , H01L23/04 , H01L23/055 , H01L23/10 , H01L23/576 , H01L25/0655 , H01L2224/16225 , H01L2224/16227 , H01L2924/01079 , H01L2924/09701 , H01L2924/15192 , H01L2924/3011 , H05K1/0275 , H05K1/0306 , H05K1/144 , H05K2201/09263 , H05K2201/10151
摘要： A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.
摘要翻译：防篡改集成电路（IC）模块包括陶瓷芯片载体; 一个或多个集成电路芯片，附接到芯片载体的顶表面; 一个陶瓷基帽结构，附着在芯片载体的顶表面上，并覆盖一个或多个集成电路芯片; 以及嵌入在所述芯片载体和所述盖结构内的导电栅格结构，所述导电栅格结构具有设置在x方向，y方向和z方向上的多个曲折线; 其中所述导电栅格结构被配置为检测穿透所述IC模块的尝试。

5. 发明授权

US07234218B2 Method for separating electronic component from organic board 有权
标题翻译：电子部件与有机电路板分离的方法
公开(公告)号：US07234218B2
公开(公告)日：2007-06-26
申请号：US10906816
申请日：2005-03-08
申请人： Mukta G. Farooq , Harvey C. Hamel
发明人： Mukta G. Farooq , Harvey C. Hamel
IPC分类号： B23P19/02
CPC分类号： H05K3/3494 , B23K1/018 , B23K2101/40 , H01L24/98 , H01L2224/81222 , H01L2224/81234 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H05K1/0212 , H05K3/3436 , H05K2203/176 , Y10T29/49144 , Y10T29/49721 , Y10T29/49815 , Y10T29/49819 , Y10T29/49821 , H01L2924/00
摘要： A method and electrical structure for separating electronic components from one another joined by solder interconnections. An electronic module is joined to a substrate via a solder interconnection, whereby the electronic module has an electrical heating component residing within a bottom layer thereof adjacent a solder interconnection. Preferably, a chip carrier is joined to a board whereby the chip carrier has an electrical mesh plane for heating adjacent the solder interconnection. Resistive heat is generated within this electrical heating component either by applying an electrical current to the electrical heating component, or by non-contact inductively heating the layer in which such electrical heating component resides to generate resistive heat within the electrical heating component. The resistive heat is transferred to the solder interconnection to allow for localized melting of the solder interconnection and removal of the electronic components from one another.
摘要翻译：一种用于将电子部件彼此分离以通过焊料互连连接的方法和电气结构。电子模块通过焊料互连连接到基板，由此电子模块具有驻留在其邻近焊料互连的底层内的电加热部件。优选地，芯片载体连接到板，由此芯片载体具有用于在焊料互连附近加热的电网平面。通过向电加热部件施加电流，或通过非接触感应加热这种电加热部件所在的层以在电加热部件内产生电阻热，在该电加热部件内产生电阻热。电阻热转移到焊料互连以允许焊料互连的局部熔化和电子部件相互之间的移除。

6. 发明授权

US07088000B2 Method and structure to wire electronic devices 失效
标题翻译：线电子器件的方法和结构
公开(公告)号：US07088000B2
公开(公告)日：2006-08-08
申请号：US10904439
申请日：2004-11-10
申请人： Michael S. Cranmer , Michael J. Domitrovits , Benjamin V. Fasano , Harvey C. Hamel , Charles T. Ryan
发明人： Michael S. Cranmer , Michael J. Domitrovits , Benjamin V. Fasano , Harvey C. Hamel , Charles T. Ryan
IPC分类号： H01L23/48 , H01L23/53 , H01L29/40
CPC分类号： H05K1/115 , H01L21/486 , H01L21/76802 , H01L21/76898 , H01L23/49827 , H01L23/49838 , H01L2924/0002 , H01L2924/3011 , H05K1/0251 , H05K3/005 , H05K2201/09609 , H05K2201/09854 , H05K2203/1476 , H01L2924/00
摘要： An integrated circuit structure and a method of manufacturing, wherein the method comprises forming a first via in an interconnect layer of the substrate, wherein the first via comprises a first size diameter; and forming a second via in the interconnect layer, wherein the second via comprises a second size diameter, the second size diameter being dimensioned larger than the first size diameter, wherein the second via comprises a non-uniform circumference, and wherein the substrate is configured in an approximately 1:1 ratio (i.e., approximately equal number) of the first and second vias. The first and second vias are laser formed or are formed by any of mechanical punching and photolithography. The second via is formed by sequentially forming multiple partially overlapping vias dimensioned and configured with the first size diameter. The first and second vias are arranged in a grid to allow for wiring of electronic devices.
摘要翻译：一种集成电路结构和制造方法，其中所述方法包括在所述衬底的互连层中形成第一通孔，其中所述第一通孔包括第一尺寸直径; 以及在所述互连层中形成第二通孔，其中所述第二通孔包括第二尺寸直径，所述第二尺寸直径的尺寸大于所述第一尺寸直径，其中所述第二通孔包括不均匀的周长，并且其中所述基板被配置以大约1:1的比例（即，大致相等的数量）第一和第二通孔。第一和第二通孔是激光成形的或通过机械冲压和光刻中的任何一种形成。第二通孔是通过顺序地形成多个部分重叠的通孔形成的，其尺寸和构造为具有第一尺寸直径。第一和第二通孔布置成格栅以允许电子设备的布线。

7. 发明授权

US06806793B2 MLC frequency selective circuit structures 失效
标题翻译： MLC频率选择电路结构
公开(公告)号：US06806793B2
公开(公告)日：2004-10-19
申请号：US10318933
申请日：2002-12-13
申请人： Harsaran S. Bhatia , Harvey C. Hamel , David C. Long , Edward R. Pillai , Christopher D. Setzer , Benjamin P. Tongue
发明人： Harsaran S. Bhatia , Harvey C. Hamel , David C. Long , Edward R. Pillai , Christopher D. Setzer , Benjamin P. Tongue
IPC分类号： H03H1104
CPC分类号： H01L23/66 , H01L23/15 , H01L23/49822 , H01L23/5227 , H01L2224/16 , H01L2924/00014 , H01L2924/1423 , H01L2924/3011 , H03H7/0115 , H03H2210/012 , H01L2224/0401
摘要： MLC (multilayer ceramic) frequency selective circuit structures are disclosed. The MLC frequency selective circuit structures have a solenoid and toroid coil geometry in a multilayer electronic package which functions as a frequency selective tuned circuit in which both the number of turns and the aspect ratio of the solenoid coil are selected to adjust the tuned frequency. In some embodiments, a plurality of such coils can be connected together to provide a selected bandwidth about a tuned center frequency.
摘要翻译：公开了MLC（多层陶瓷）频率选择电路结构。 MLC频率选择电路结构在多层电子封装中具有螺线管和环形线圈几何形状，其作为频率选择调谐电路，其中选择螺线管线圈的匝数和纵横比，以调节调谐频率。在一些实施例中，多个这样的线圈可以连接在一起以提供关于调谐中心频率的选定带宽。

8. 发明授权

US6023407A Structure for a thin film multilayer capacitor 失效
标题翻译：薄膜多层电容器的结构
公开(公告)号：US6023407A
公开(公告)日：2000-02-08
申请号：US31235
申请日：1998-02-26
申请人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
IPC分类号： H01L27/04 , H01G4/30 , H01G4/33 , H01L21/02 , H01L21/822 , H01G4/005 , H01G4/228
CPC分类号： H01L28/40 , H01G4/306 , Y10T29/435
摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译：提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。还提出了一种用于制造中介层薄膜电容器的方法。为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10μm的厚的第一金属层沉积在衬底上然后施加剩余的薄膜，包括电介质膜和第二金属层。第一金属层包括Pt或其它电极金属，或Pt，Cr和Cu金属的组合以及扩散阻挡层。另外的Ti层可以用于附着增强。对于Cr层，第一金属层的厚度约为：200A; Cu层为0.5-10μm; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。

9. 发明授权

US06216324B1 Method for a thin film multilayer capacitor 失效
标题翻译：薄膜多层电容器的方法
公开(公告)号：US06216324B1
公开(公告)日：2001-04-17
申请号：US09382536
申请日：1999-08-25
申请人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
IPC分类号： H01G4002
CPC分类号： H01L28/40 , H01G4/306 , Y10T29/435
摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译：提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。还提出了一种用于制造中介层薄膜电容器的方法。为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10毫米的厚的第一金属层沉积在衬底上，衬底上沉积然后施加包括电介质膜和第二金属层的剩余薄膜。第一金属层由Pt或其他电极金属或Pt，Cr和Cu金属的组合以及扩散阻挡层组成。另外的Ti层可以用于附着增强。对于Cr层，第一金属层的厚度约为：200A; 铜层为0.5-10毫米; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。

10. 发明授权

US6090633A Multiple-plane pair thin-film structure and process of manufacture 失效
标题翻译：多平面对薄膜结构及制造工艺
公开(公告)号：US6090633A
公开(公告)日：2000-07-18
申请号：US401098
申请日：1999-09-22
申请人： Roy Yu , Chandrika Prasad , John R. Pennacchia , Harvey C. Hamel
发明人： Roy Yu , Chandrika Prasad , John R. Pennacchia , Harvey C. Hamel
IPC分类号： H01L21/48 , H01L23/538 , H05K3/40 , H05K3/46 , H01L23/02 , H01L23/053 , H01L23/12 , H01L29/40 , G01R21/66
CPC分类号： H05K3/462 , H01L21/485 , H01L23/5382 , H01L23/5385 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H05K2201/0305 , H05K2203/016 , H05K2203/063 , H05K2203/162 , H05K3/4038 , H05K3/4623 , H05K3/467 , H05K3/4688
摘要： A multiple plane pair thin-film structure and a process for the manufacture of that structure. The multiple plane pair thin-film structure is of modular design and manufacture, such that each module comprising the structure is manufactured and tested individually before assembly. The thin film wiring structure is comprised of a plurality of true plane pair thin-film structures. Each such plane pair thin-film structure is manufactured as a module, the functionality of which can be tested for conformity to applicable specifications. Each module is designed and fabricated as a plane pair thin-film structure.
摘要翻译：多平面对薄膜结构和制造该结构的方法。多平面对薄膜结构具有模块化设计和制造，使得包括该结构的每个模块在组装之前单独制造和测试。薄膜布线结构由多个真平面对薄膜结构构成。每个这样的平面对薄膜结构被制造为模块，其功能可以被测试以符合适用的规范。每个模块设计和制造为平面对薄膜结构。

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