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1. 发明授权

US06893979B2 Method for improved plasma nitridation of ultra thin gate dielectrics 失效
标题翻译：用于改进超薄栅极电介质等离子体氮化的方法
公开(公告)号：US06893979B2
公开(公告)日：2005-05-17
申请号：US09809663
申请日：2001-03-15
申请人： Mukesh V. Khare , Christopher P. D'Emic , Thomas T. Hwang , Paul C. Jamison , James J. Quinlivan , Beth A. Ward
发明人： Mukesh V. Khare , Christopher P. D'Emic , Thomas T. Hwang , Paul C. Jamison , James J. Quinlivan , Beth A. Ward
IPC分类号： H01L21/265 , H01L21/28 , H01L21/314 , H01L21/318 , H01L29/51 , H01L29/78 , H01L21/31 , H01L21/469
CPC分类号： H01L29/518 , H01L21/28202 , H01L21/2822 , H01L21/3144
摘要： A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.
摘要翻译：一种用于形成用于集成电路器件的栅极电介质的方法。在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

2. 发明授权

US07109559B2 Nitrided ultra thin gate dielectrics 失效
标题翻译：氮化超薄栅极电介质
公开(公告)号：US07109559B2
公开(公告)日：2006-09-19
申请号：US10982999
申请日：2004-11-05
申请人： Mukesh V. Khare , Christopher P. D'Emic , Thomas T. Hwang , Paul C. Jamison , James J. Quinlivan , Beth A. Ward
发明人： Mukesh V. Khare , Christopher P. D'Emic , Thomas T. Hwang , Paul C. Jamison , James J. Quinlivan , Beth A. Ward
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/518 , H01L21/28202 , H01L21/2822 , H01L21/3144
摘要： A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.
摘要翻译：一种用于形成用于集成电路器件的栅极电介质的方法。在本发明的示例性实施例中，该方法包括在基底材料上形成初始氧氮化物层，该氮氧化物层具有初始物理厚度。然后对初始氧氮化物层进行等离子体氮化处理，等离子体氮化导致最终的氧氮化物层具有最终的物理厚度。

3. 发明授权

US07115959B2 Method of forming metal/high-k gate stacks with high mobility 有权
公开(公告)号：US07115959B2
公开(公告)日：2006-10-03
申请号：US10873733
申请日：2004-06-22
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evengi Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph P. Shepard, Jr. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evengi Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph P. Shepard, Jr. , Sufi Zafar
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

4. 发明授权

US08153514B2 Method of forming metal/high-κ gate stacks with high mobility 有权
标题翻译：金属/高分子金属成型方法移动性高的门栈
公开(公告)号：US08153514B2
公开(公告)日：2012-04-10
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, Jr. , Sufi Zafar
IPC分类号： H01L21/3205
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

5. 发明申请

US20080293259A1 METHOD OF FORMING METAL/HIGH-k GATE STACKS WITH HIGH MOBILITY 有权
标题翻译：形成具有高移动性的金属/高k栅极堆叠的方法
公开(公告)号：US20080293259A1
公开(公告)日：2008-11-27
申请号：US12187767
申请日：2008-08-07
申请人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
发明人： Wanda Andreoni , Alessandro C. Callegari , Eduard A. Cartier , Alessandro Curioni , Christopher P. D'Emic , Evgeni Gousev , Michael A. Gribelyuk , Paul C. Jamison , Rajarao Jammy , Dianne L. Lacey , Fenton R. McFeely , Vijay Narayanan , Carlo A. Pignedoli , Joseph F. Shepard, JR. , Sufi Zafar
IPC分类号： H01L21/263
CPC分类号： H01L21/28176 , H01L29/4908 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6656 , H01L29/66575 , H01L29/66772 , H01L29/7833 , H01L29/78684
摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.
摘要翻译：本发明提供具有高移动性和低界面电荷的栅叠层结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间。本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。本发明中使用的高温退火提供了具有大约8×10 10电荷/ cm 2或更小的电荷泵浦的界面状态密度，约250cm 2 / s以上的峰值迁移率和基本上没有约6.0×10 12反相电荷/ cm 2以上的迁移率降解。

6. 发明申请

US20130049199A1 SILICIDATION OF DEVICE CONTACTS USING PRE-AMORPHIZATION IMPLANT OF SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：使用半导体基板的预加工植入物进行器件接触的硅化
公开(公告)号：US20130049199A1
公开(公告)日：2013-02-28
申请号：US13222469
申请日：2011-08-31
申请人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
发明人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
IPC分类号： H01L23/532 , H01L21/336 , H01L21/768
CPC分类号： H01L21/26506 , H01L21/28518 , H01L29/00 , H01L29/665 , H01L29/7833
摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.
摘要翻译：具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。例如，用于形成硅化物的方法包括用非晶化物质注入硅层以在硅层中形成非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。然后进行自杀处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。

7. 发明授权

US08557670B1 SOI lateral bipolar junction transistor having a wide band gap emitter contact 有权
标题翻译：具有宽带隙发射极接触的SOI横向双极结型晶体管
公开(公告)号：US08557670B1
公开(公告)日：2013-10-15
申请号：US13605253
申请日：2012-09-06
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L21/8222
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

8. 发明申请

US20130256757A1 SOI LATERAL BIPOLAR JUNCTION TRANSISTOR HAVING A WIDE BAND GAP EMITTER CONTACT 审中-公开
标题翻译：具有宽带带隙发射体接触的SOI侧向双极晶体管
公开(公告)号：US20130256757A1
公开(公告)日：2013-10-03
申请号：US13433537
申请日：2012-03-29
申请人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
发明人： Jin Cai , Kevin K. Chan , Christopher P. D'Emic , Tak H. Ning , Dae-Gyu Park
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/42304 , H01L29/66242 , H01L29/66272 , H01L29/7322 , H01L29/7371
摘要： A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
摘要翻译：在绝缘体上半导体衬底上形成横向异质结双极晶体管，该衬底包括具有第一带隙和第一导电类型掺杂的第一半导体材料的顶部半导体部分。形成外部基座和基座的堆叠，使得叠层跨越顶部半导体部分。在堆叠周围形成介电隔离件。执行第二导电类型的掺杂剂的离子注入以掺杂未被叠层和电介质间隔物掩蔽的顶部半导体部分的区域，由此形成发射极区域和集电极区域。具有大于第一带隙的第二带隙并且具有第二导电类型的掺杂的第二半导体材料被选择性地沉积在发射极区域和集电极区域上，以分别形成发射极接触区域和集电极接触区域。

9. 发明申请

US20130049200A1 SILICIDATION OF DEVICE CONTACTS USING PRE-AMORPHIZATION IMPLANT OF SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：使用半导体基板的预加工植入物进行器件接触的硅化
公开(公告)号：US20130049200A1
公开(公告)日：2013-02-28
申请号：US13598686
申请日：2012-08-30
申请人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
发明人： Paul R. Besser , Roy A. Carruthers , Christopher P. D'Emic , Christian Lavoie , Conal E. Murray , Kazuya Ohuchi , Christopher Scerbo , Bin Yang
IPC分类号： H01L29/43
CPC分类号： H01L21/26506 , H01L21/28518 , H01L29/00 , H01L29/665 , H01L29/7833
摘要： Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to fond an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A silicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.
摘要翻译：具有改进的稀土硅化物形态的硅化技术用于制造半导体器件触点。例如，用于形成硅化物的方法包括将具有非晶化物质的硅层注入以在硅层中融合非晶硅区域，并在与非晶硅区域接触的硅层上沉积稀土金属膜。然后进行硅化处理以组合稀土金属膜和非晶硅区域，以在硅层上形成硅化物膜。

10. 发明授权

US06350321B1 UHV horizontal hot wall cluster CVD/growth design 失效
标题翻译：特高压水平热壁簇CVD /生长设计
公开(公告)号：US06350321B1
公开(公告)日：2002-02-26
申请号：US09207353
申请日：1998-12-08
申请人： Kevin K. Chan , Christopher P. D'Emic , Raymond M. Sicina , Paul M. Kozlowski , Margaret Manny , Sandip Tiwari
发明人： Kevin K. Chan , Christopher P. D'Emic , Raymond M. Sicina , Paul M. Kozlowski , Margaret Manny , Sandip Tiwari
IPC分类号： C23C1600
CPC分类号： H01L21/67225 , C23C14/56
摘要： A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.
摘要翻译：簇系统控制在硅衬底上沉积或生长的膜的界面性质。该系统包括多个水平石英腔或管，每个水平的石英腔或管可以容纳大量的晶片，传送室和装载/卸载室。可以在不同环境空气的情况下，在不同的管中顺序执行若干工艺步骤。传输室连接它们，并允许晶片在绝对控制的特高压环境中从一个管到另一个管输送，将任何污染（例如H 2 O）限制到小于单层。此外，每个管可以泵送到特高压压力状态，以避免管之间的进一步交叉污染或产生颗粒。由于某些过程需要升高的温度，因此将所有晶片垂直放置在石英舟上，以防止垂直炉中出现任何晶片下垂。此外，在将任何晶片放入转移室之前，它们被装载到与环境空气的唯一连接的装载/卸载室中，以被清除和泵送，以使颗粒和污染物最小化。

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