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1. 发明授权

US07403426B2 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US07403426B2
公开(公告)日：2008-07-22
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
IPC分类号： G11C11/34
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

2. 发明授权

US07230842B2 Memory cell having p-type pass device 有权
标题翻译：具有p型通过装置的存储单元
公开(公告)号：US07230842B2
公开(公告)日：2007-06-12
申请号：US11225912
申请日：2005-09-13
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Nam Sung Kim , Yibin Ye , Vivek K. De , Kevin Zhang , Bo Zheng
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Nam Sung Kim , Yibin Ye , Vivek K. De , Kevin Zhang , Bo Zheng
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , Y10S257/903
摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，一种装置包括耦合在单元电压节点和存储节点之间的第一p型装置，耦合在存储节点和参考电压节点之间的n型装置和耦合在第二p型装置之间存储节点响应于选择线上的信号到位线。衬底中的形成第一p型器件和第二p型器件的扩散区域的至少一侧基本对齐。还公开了其他实施例。

3. 发明申请

US20060268626A1 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US20060268626A1
公开(公告)日：2006-11-30
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
IPC分类号： G11C7/10
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

4. 发明申请

US20070058419A1 Memory cell having p-type pass device 有权
公开(公告)号：US20070058419A1
公开(公告)日：2007-03-15
申请号：US11225912
申请日：2005-09-13
申请人： Muhammad Khellah , Dinesh Somasekhar , Nam Kim , Yibin Ye , Vivek De , Kevin Zhang , Bo Zheng
发明人： Muhammad Khellah , Dinesh Somasekhar , Nam Kim , Yibin Ye , Vivek De , Kevin Zhang , Bo Zheng
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , Y10S257/903
摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

5. 发明授权

US06181608B2 Dual Vt SRAM cell with bitline leakage control 有权
标题翻译：双Vt SRAM单元，具有位线泄漏控制
公开(公告)号：US06181608B2
公开(公告)日：2001-01-30
申请号：US09261915
申请日：1999-03-03
申请人： Ali Keshavarzi , Kevin Zhang , Yibin Ye , Vivek K. De
发明人： Ali Keshavarzi , Kevin Zhang , Yibin Ye , Vivek K. De
IPC分类号： G11C1134
CPC分类号： G11C11/412 , G11C11/418
摘要： In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines. In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.
摘要翻译：在一些实施例中，本发明包括包括位线和位线＃，字线和存储器单元的集成电路。每个对应于一个字线的存储单元分别包括分别耦合在第一和第二存储节点之间的第一和第二传输晶体管，位线和位线＃分别耦合到第一和第二通道的栅极晶体管。存储单元包括交叉耦合在第一和第二存储节点之间的第一和第二反相器，其中第一和第二传输晶体管每个具有比第一和第二反相器的晶体管更低的阈值电压。耦合到字线的字线电压控制电路有选择地控制字线上的字线信号。在一些实施例中，字线电压控制电路为对应于被选择要读取的存储器单元选择的字线断言字线信号，并驱动不对应于所选存储单元的字线的字线信号。

6. 发明授权

US07981756B2 Common plate capacitor array connections, and processes of making same 有权
标题翻译：普通板电容阵列连接及其制作工艺
公开(公告)号：US07981756B2
公开(公告)日：2011-07-19
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译：形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。该过程包括将电容器单元边界的第一高度降低到第二高度。普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

7. 发明申请

US20100155887A1 Common plate capacitor array connections, and processes of making same 有权
标题翻译：普通板电容阵列连接及其制作工艺
公开(公告)号：US20100155887A1
公开(公告)日：2010-06-24
申请号：US12317656
申请日：2008-12-22
申请人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
发明人： Nick Lindert , Brian Doyle , Dinesh Somasekhar , Christopher J. Jezewski , Swaminathan Sivakumar , Kevin Zhang , Stephen Wu
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L27/101 , H01L28/90
摘要： A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.
摘要翻译：形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。该过程包括将电容器单元边界的第一高度降低到第二高度。普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

8. 发明授权

US08406073B1 Hierarchical DRAM sensing 有权
标题翻译：分层DRAM感知
公开(公告)号：US08406073B1
公开(公告)日：2013-03-26
申请号：US12928948
申请日：2010-12-22
申请人： Dinesh Somasekhar , Gunjan Pandya , Kevin Zhang , Fatih Hamzaoglu , Balaji Srinivasan , Swaroop Ghosh , Meterelliyoz Mesut
发明人： Dinesh Somasekhar , Gunjan Pandya , Kevin Zhang , Fatih Hamzaoglu , Balaji Srinivasan , Swaroop Ghosh , Meterelliyoz Mesut
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C7/065 , G11C7/08 , G11C11/4091 , G11C11/4094
摘要： A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.
摘要翻译：采用本地位线对和全局位线的分级DRAM感测装置和方法。字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。选择本地位线之一用于耦合到全局位线和全局读出放大器。集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。

9. 发明申请

US20060002177A1 Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength 有权
标题翻译：具有动态可变p沟道金属氧化物半导体（PMOS）强度的六晶体管（6T）静态随机存取存储器（SRAM）
公开(公告)号：US20060002177A1
公开(公告)日：2006-01-05
申请号：US10883609
申请日：2004-06-30
申请人： Bo Zheng , Kevin Zhang , Fatih Hamzaoglu , Yih Wang
发明人： Bo Zheng , Kevin Zhang , Fatih Hamzaoglu , Yih Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C11/412
摘要： In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).
摘要翻译：在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

10. 发明授权

US07177176B2 Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength 有权
标题翻译：具有动态可变p沟道金属氧化物半导体（PMOS）强度的六晶体管（6T）静态随机存取存储器（SRAM）
公开(公告)号：US07177176B2
公开(公告)日：2007-02-13
申请号：US10883609
申请日：2004-06-30
申请人： Bo Zheng , Kevin Zhang , Fatih Hamzaoglu , Yih (Eric) Wang
发明人： Bo Zheng , Kevin Zhang , Fatih Hamzaoglu , Yih (Eric) Wang
IPC分类号： G11C11/00 , G11C5/14 , G11C7/10
CPC分类号： G11C11/417 , G11C11/412
摘要： In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).
摘要翻译：在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

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