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1. 发明申请

US20070075738A1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US20070075738A1
公开(公告)日：2007-04-05
申请号：US11502572
申请日：2006-08-11
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。所述逻辑单元中的至少一个具有：包括MIS晶体管的标准单元，所述标准单元包括输入来自前一级的输出信号的输入端作为输入信号和输出端，所述标准单元执行基于所述输入信号进行预定的逻辑运算，并输出所述逻辑运算的结果作为来自所述输出端子的输出信号; 设置在标准单元的输出端子与第一电源电压之间的第一导电型第一MIS晶体管，所述第一MIS晶体管包括输入电路控制信号的控制端子和提供电路控制信号的第一MIS晶体管基于电路控制信号向标准单元的输出端施加第一电源电压，以使标准单元进入操作停止状态; 以及设置在所述标准单元和第二电源电压之间的第二导电型第二MIS晶体管，所述第二MIS晶体管包括输入所述电路控制信号的控制端子，所述第二MIS晶体管切断漏电流的基于电路控制信号的标准单元中的MIS晶体管，以使标准单元进入操作停止状态。

2. 发明申请

US20080238485A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20080238485A1
公开(公告)日：2008-10-02
申请号：US12132428
申请日：2008-06-03
申请人： Mototsugu HAMADA , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu HAMADA , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K19/096
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。第一导电型第一MIS晶体管，设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管，基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

3. 发明授权

US07397271B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07397271B2
公开(公告)日：2008-07-08
申请号：US11502572
申请日：2006-08-11
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells has: a standard cell which includes a MIS transistor, the standard cell including an input terminal to which an output signal from a previous stage is inputted as an input signal and an output terminal, and the standard cell performing a predetermined logic operation based on the input signal and outputting a result of the logic operation as an output signal from the output terminal; a first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state; and a second conductivity-type second MIS transistor which is provided between the standard cell and a second power supply voltage, the second MIS transistor including a control terminal to which the circuit control signal is inputted, and the second MIS transistor cutting off a leakage current of the MIS transistor in the standard cell based on the circuit control signal in order to bring the standard cell into the operation-stopped state.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。所述逻辑单元中的至少一个具有：包括MIS晶体管的标准单元，所述标准单元包括输入来自前一级的输出信号的输入端作为输入信号和输出端，所述标准单元执行基于所述输入信号进行预定的逻辑运算，并输出所述逻辑运算的结果作为来自所述输出端子的输出信号; 设置在标准单元的输出端子与第一电源电压之间的第一导电型第一MIS晶体管，所述第一MIS晶体管包括输入电路控制信号的控制端子和提供电路控制信号的第一MIS晶体管基于电路控制信号向标准单元的输出端施加第一电源电压，以使标准单元进入操作停止状态; 以及设置在所述标准单元和第二电源电压之间的第二导电型第二MIS晶体管，所述第二MIS晶体管包括输入所述电路控制信号的控制端子，所述第二MIS晶体管切断漏电流的基于电路控制信号的标准单元中的MIS晶体管，以使标准单元进入操作停止状态。

4. 发明授权

US08067962B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08067962B2
公开(公告)日：2011-11-29
申请号：US12554570
申请日：2009-09-04
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K19/096
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。第一导电型第一MIS晶体管，其设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管，基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

5. 发明申请

US20100066419A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20100066419A1
公开(公告)日：2010-03-18
申请号：US12554570
申请日：2009-09-04
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03L7/00
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。第一导电型第一MIS晶体管，设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管，基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

6. 发明授权

US07602211B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07602211B2
公开(公告)日：2009-10-13
申请号：US12132428
申请日：2008-06-03
申请人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
发明人： Mototsugu Hamada , Tsuyoshi Nishikawa , Toshiyuki Furusawa
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/17736 , H03K19/1736 , H03K19/17728 , H03K19/1778
摘要： A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
摘要翻译：半导体集成电路器件具有包括串联连接的一个或多个逻辑单元的组合逻辑电路。逻辑单元中的至少一个包括标准单元，其包括MIS晶体管，作为输入信号输入来自前一级的输出信号的输入端子和输出端子。第一导电型第一MIS晶体管，设置在标准单元的输出端子与第一电源电压之间，第一MIS晶体管包括输入电路控制信号的控制端子，以及第一MIS晶体管，基于电路控制信号向标准单元的输出端子提供第一电源电压，以使标准单元进入操作停止状态。第二导电型第二MIS晶体管截止在标准单元中的MIS晶体管的漏电流。

7. 发明授权

US07216329B2 Automatic circuit design apparatus, method for automatically designing a circuit, and computer program product for executing an application for an automatic circuit design apparatus 失效
标题翻译：自动电路设计装置，用于自动设计电路的方法，以及用于执行自动电路设计装置的应用的计算机程序产品
公开(公告)号：US07216329B2
公开(公告)日：2007-05-08
申请号：US10816640
申请日：2004-04-02
申请人： Takeshi Kitahara , Masaaki Yamada , Naoyuki Kawabe , Masahiro Kanazawa , Katsuhiro Seta , Toshiyuki Furusawa
发明人： Takeshi Kitahara , Masaaki Yamada , Naoyuki Kawabe , Masahiro Kanazawa , Katsuhiro Seta , Toshiyuki Furusawa
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5068
摘要： An automatic circuit design apparatus includes a setting module configured to set an upper limit electric potential of a virtual ground line in a circuit to be designed, by use of a cell library for low-threshold cells, a cell library for high-threshold cells, and information of the circuit to be designed. A layout generator is configured to generate a layout based on the information, the cell library for low-threshold cells, and the cell library for high-threshold cells.
摘要翻译：一种自动电路设计装置，包括：设置模块，被配置为通过使用用于低阈值单元的单元库，设置用于高阈值单元的单元库来设置要设计的电路中的虚拟接地线的上限电位; 以及要设计的电路的信息。布局生成器被配置为基于信息生成布局，低阈值单元的单元库以及用于高阈值单元的单元库。

8. 发明授权

US07109771B2 Semiconductor integrated circuit with reduced leakage current 失效
公开(公告)号：US07109771B2
公开(公告)日：2006-09-19
申请号：US10946398
申请日：2004-09-21
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H03K3/356
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

9. 发明申请

US20050035803A1 Semiconductor integrated circuit with reduced leakage current 失效
公开(公告)号：US20050035803A1
公开(公告)日：2005-02-17
申请号：US10948349
申请日：2004-09-23
申请人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
发明人： Toshiyuki Furusawa , Daisuke Sonoda , Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Hidemasa Zama , Masahiro Kanazawa
IPC分类号： H01L21/822 , H01L27/04 , H03K19/00 , H03K3/02
CPC分类号： H03K19/0016
摘要： A combination circuit is switched between an active state where power is supplied thereto in response to a control signal and an inactive state where power thereto is interrupted. A flip-flop circuit connected to an input terminal of the combination circuit stores an output signal of the combination circuit in response to a clock signal. The combination circuit is set to an operative state by the control signal immediately before the flip-flop circuit operates in response to the clock signal.

10. 发明授权

US06798238B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06798238B2
公开(公告)日：2004-09-28
申请号：US10372937
申请日：2003-02-26
申请人： Munehito Mushiga , Katsuhiro Seta , Takeshi Yoshimoto , Toshiyuki Furusawa
发明人： Munehito Mushiga , Katsuhiro Seta , Takeshi Yoshimoto , Toshiyuki Furusawa
IPC分类号： H03L706
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit, comprises a first reference voltage line; a second reference voltage line; a plurality of single logic circuits each including a plurality of transistors; a first switch having a first transistor provided between said first reference voltage line and said logic circuits, said first transistor having a higher threshold voltage than that of transistors in the logic circuits; and a second switch having a second transistor provided a between said second transistor having a higher threshold voltage than that of transistors in the logic circuits, said first and second switches being turned on when at least one of said single logic circuits is in operation, while said first and second switches being turned off when all of said single logic circuits are in standby state.
摘要翻译：一种半导体集成电路，包括第一参考电压线; 第二参考电压线;多个单个逻辑电路，每个包括多个晶体管; 第一开关，其具有设置在所述第一参考电压线和所述逻辑电路之间的第一晶体管，所述第一晶体管的阈值电压高于逻辑电路中的晶体管; 以及具有第二晶体管的第二开关，所述第二晶体管设置在所述第二晶体管之间，具有比所述逻辑电路中的晶体管更高的阈值电压，所述第一和第二开关在所述单个逻辑电路中的至少一个处于操作时导通，同时当所有单个逻辑电路都处于待机状态时，所述第一和第二开关断开。

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