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    • 1. 发明授权
    • Semiconductor circuit and semiconductor device
    • 半导体电路和半导体器件
    • US08803561B2
    • 2014-08-12
    • US13228903
    • 2011-09-09
    • Motoki ImanishiKenji SakaiYoshikazu TanakaKyouko Oyama
    • Motoki ImanishiKenji SakaiYoshikazu TanakaKyouko Oyama
    • H03K3/00
    • H03K17/162H01L2924/0002H01L2924/00
    • A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor.
    • 本发明的半导体电路包括:用于响应于ON驱动信号对接通驱动电荷进行充电的电容器;响应于OFF驱动信号而对驱动电荷进行充电的电容器;产生第一触发信号的信号产生电路 响应于ON驱动信号,产生响应于OFF驱动信号产生第二触发信号的信号发生电路,用于响应于第二触发信号对ON驱动电荷进行放电的放电电路,以及用于放电的放电电路 OFF驱动电荷响应于第一触发信号。 利用这种结构,可以提供一种具有通用故障防止功能的半导体电路和半导体器件,通过该功能可以防止由于dV / dt引起的故障,而不受任何外部因素的影响。
    • 2. 发明授权
    • Power semiconductor device including a bootstrap compensation circuit
    • 功率半导体器件,包括自举补偿电路
    • US08724357B2
    • 2014-05-13
    • US13010178
    • 2011-01-20
    • Motoki ImanishiKenji SakaiYoshikazu Tanaka
    • Motoki ImanishiKenji SakaiYoshikazu Tanaka
    • H02M7/5387H02M1/084
    • H02M1/08H03K17/063
    • A power semiconductor device comprises: high side and low side switching elements; high side and low side drive circuits; a bootstrap capacitor supplying a drive voltage to the high side drive circuit and having a first terminal connected to a connection point between the high side switching element and the low side switching element and a second terminal connected to a power supply terminal of the high side drive circuit; a bootstrap diode having an anode connected to a power supply and a cathode connected to the second terminal and supplying a current from the power supply to the second terminal; a floating power supply; and a bootstrap compensation circuit supplying a current from the floating power supply to the second terminal, when the high side drive circuit turns ON the high side switching element and the low side drive circuit turns OFF the low side switching element.
    • 功率半导体器件包括:高侧和低侧开关元件; 高侧和低侧驱动电路; 向高侧驱动电路供给驱动电压并具有与高侧开关元件和低侧开关元件之间的连接点连接的第一端子的自举电容器和连接到高侧驱动器的电源端子的第二端子 电路 引导二极管,其具有连接到电源的阳极和连接到第二端子的阴极,并且将电流从电源提供给第二端子; 浮动电源; 以及当所述高侧驱动电路导通所述高侧开关元件并且所述低侧驱动电路使所述低侧开关元件断开时,从所述浮动电源向所述第二端子供给电流的自举补偿电路。
    • 3. 发明授权
    • Inverse level shift circuit
    • 反电平移位电路
    • US08779830B2
    • 2014-07-15
    • US13802576
    • 2013-03-13
    • Takaki NakashimaMotoki ImanishiKenji Sakai
    • Takaki NakashimaMotoki ImanishiKenji Sakai
    • H03L5/00
    • H03K17/063H03K2217/0063
    • A voltage conversion mask signal generation circuit generates a first main signal and a first mask signal by converting an output signal of the first transistor to a low-side voltage, and generating a second main signal and a second mask signal by converting an output signal of the second transistor to a low-side voltage. A mask signal generation circuit generating a third mask signal with higher sensitivity than the first and second mask signals with respect to a fluctuation in the high-side reference potential. A mask logical circuit generating a fourth mask signal by performing a AND operation between the first mask signal and the second mask signal, and masking the first and second main signals with the third and fourth mask signals; and a SR flip flop circuit generating the output signal from the masked first and second main signals.
    • 电压转换掩模信号产生电路通过将第一晶体管的输出信号转换为低侧电压来产生第一主信号和第一屏蔽信号,并且通过将第一主信号和第二屏蔽信号的输出信号 第二晶体管为低端电压。 掩模信号生成电路相对于高侧基准电位的波动产生比第一和第二掩模信号高的灵敏度的第三掩模信号。 一种掩模逻辑电路,通过在第一屏蔽信号和第二屏蔽信号之间执行“与”运算,并用第三和第四屏蔽信号屏蔽第一和第二主信号来产生第四屏蔽信号; 以及SR触发器电路,从被掩蔽的第一和第二主信号产生输出信号。
    • 6. 发明授权
    • Communication device, communication method, and computer usable medium
    • 通信设备,通信方式和计算机可用介质
    • US07546536B2
    • 2009-06-09
    • US10672478
    • 2003-09-26
    • Motoki Imanishi
    • Motoki Imanishi
    • G06F3/00G06F3/048G06F17/21
    • A63F13/87A63F13/12A63F13/22A63F13/30A63F2300/572H04L12/1827
    • A letter string editing unit of a communication device receives an edit instruction for a letter string, and edits a letter string in accordance with the instruction. A decide input reception unit receives a decide instruction for the letter string together with operation strength. When the decide instruction is received, a sending unit sends a sender side message specifying the edited letter string and strength information associated with the operation strength to another communication device. A reception unit receives a receiver side message specifying a letter string to be displayed and strength information from another communication device. A font acquiring unit acquires information of a font having a size pre-associated with the specified strength information. A display image generation unit generates a display image by depicting the specified letter string in accordance with the acquired font information. A display unit displays the generated display image.
    • 通信装置的字母串编辑单元接收字母串​​的编辑指令,并根据该指令编辑字母串。 决定输入接收单元接收字母串​​的决定指令以及操作强度。 当接收到决定指令时,发送单元向另一个通信设备发送指定与操作强度相关联的编辑字母串和强度信息的发送方消息。 接收单元从另一通信设备接收指定要显示的字母串和强度信息的接收器侧消息。 字体获取单元获取具有与指定强度信息预先关联的尺寸的字体的信息。 显示图像生成单元通过根据获取的字体信息描绘指定的字母串来生成显示图像。 显示单元显示所生成的显示图像。