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    • 3. 发明申请
    • PULSE WAVE DETECTOR
    • 脉冲波检测器
    • US20110237965A1
    • 2011-09-29
    • US13047243
    • 2011-03-14
    • Takuya HayashiKatsumi ImadaSusumu Fukushima
    • Takuya HayashiKatsumi ImadaSusumu Fukushima
    • A61B5/02
    • A61B5/02416
    • A pulse wave detector includes a) a light source repeatedly turned on and off, b) a light receiving element for receiving light, and c) an arithmetic processor for processing an output value acquired through the light receiving element. The arithmetic processor performs arithmetic processing for calculating the difference between a first output value acquired through the light receiving element when the light source is turned on and a second output value acquired through the light receiving element when the light source is turned off. With this structure, a pulse wave detector capable of detecting pulse waves even under the conditions where external light intensity varies can be provided.
    • 一种脉波检测器,包括a)重复打开和关闭的光源,b)用于接收光的光接收元件,以及c)用于处理通过光接收元件获取的输出值的运算处理器。 算术处理器执行算术处理,用于计算当光源打开时通过光接收元件获取的第一输出值与当光源关闭时通过光接收元件获取的第二输出值之间的差异。 利用这种结构,可以提供即使在外部光强度变化的条件下能够检测脉搏波的脉波检测器。
    • 6. 发明申请
    • Surface-coated cermet cutting tool with a hard coating layer exhibiting excellent chipping resistance
    • 表面涂层金属陶瓷切削工具,具有优异的耐崩裂性的硬涂层
    • US20050214579A1
    • 2005-09-29
    • US10999222
    • 2004-11-24
    • Fumio TsushimaTakuya HayashiTakatoshi Oshika
    • Fumio TsushimaTakuya HayashiTakatoshi Oshika
    • C23C16/02C23C16/30C23C16/40C23C30/00B32B9/00
    • C23C16/30C23C16/0272C23C16/40C23C16/403C23C30/005Y10T428/24975Y10T428/265Y10T428/30
    • A surface-coated cermet cutting tool with a hard-coating layer having excellent chipping resistance. The hard coating layer is formed on a surface of a tool substrate that constitutes the surface-coated cermet cutting tool. The hard coating layer includes(a) as the lower layer, a titanium compound layer having at least one or two of a titanium carbide layer, a titanium nitride layer, a titanium carbonitride layer, a titanium carboxide layer and a titanium oxycarbonitride layer, and (b) as the upper layer, a heat-transformed α-type Al—Zr oxide layer formed by carrying out a heat-transforming treatment in a state that a titanium oxide layer satisfying the composition formula: TiOY, ¥ The heat-transformed α-type Al—Zr oxide layer is chemically deposited on a surface of an Al—Zr oxide layer having a κ-type or θ-type crystal structure and satisfying the composition formula: (Al1−XZrX)2O3 to transform the crystal structure of the Al—Zr oxide layer having the κ-type or θ-type crystal structure into an α-type crystal structure.
    • 具有优异的耐崩裂性的硬涂层的表面被覆金属陶瓷切削工具。 该硬涂层形成在构成表面被覆金属陶瓷切削工具的工具基板的表面上。 硬涂层包括(a)作为下层,具有碳化钛层,氮化钛层,碳氮化钛层,钛羧化物层和钛碳氮氧化物层中的至少一种或两种的钛化合物层,以及 (b)作为上层,通过在满足以下组成式的氧化钛层的状态下进行热转化处理而形成的热转变的α型Al-Zr氧化物层: 热变换的α型Al-Zr氧化物层化学沉积在具有κ型或θ型晶体结构的Al-Zr氧化物层的表面上,并且满足以下组成式:(A1 < 1-X X 2 3 ,以使具有κ- 型或θ型晶体结构成为α型晶体结构。
    • 8. 发明申请
    • Static random acess memory device
    • 静态随机存取存储器
    • US20080278993A1
    • 2008-11-13
    • US12149500
    • 2008-05-02
    • Takuya HayashiYoshisato Yokoyama
    • Takuya HayashiYoshisato Yokoyama
    • G11C11/00G11C8/16
    • G11C11/412G11C8/16
    • Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P1 and P2 and gate electrodes of the load transistors PL1 and PL2 are connected at the node 1 and the node 2. A source electrode of the additional transistor P1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S1 and S2 to the H level in other times than data write so that the additional transistor P1 or P2 compensates the load transistor PL1 or PL2, thereby increasing the static margin. In data write, the additional transistor control circuit sets the control signals S1 and S2 to the low level, thereby preventing the additional transistors from hindering the data write, and thus increasing the write margin.
    • 作为PMOS晶体管的附加晶体管P 1和P 2连接到作为PMOS晶体管的负载晶体管PL 1和PL 2,使得附加晶体管P 1和P 2的漏极和负载晶体管PL 1和PL 2的漏电极 连接在节点1和节点2,而附加晶体管P 1和P 2的栅电极和负载晶体管PL 1和PL 2的栅电极在节点1和节点2连接。 附加晶体管P 1的源电极连接到为每列提供的附加晶体管控制电路。 附加晶体管控制电路在数据写入的其他时间中将控制信号S1和S2设置为H电平,使得附加晶体管P 1或P 2补偿负载晶体管PL 1或PL 2,从而增加静态裕度。 在数据写入时,附加晶体管控制电路将控制信号S1和S2设置为低电平,从而防止附加晶体管妨碍数据写入,从而增加写入裕度。
    • 9. 发明申请
    • PROCESS MIGRATION METHOD COMPUTER AND SYSTEM
    • 过程移动方法计算机和系统
    • US20080077706A1
    • 2008-03-27
    • US11943005
    • 2007-11-20
    • Seiji MaedaKiyoko SatoNobuo SakiyamaHirokuni YanoTakuya Hayashi
    • Seiji MaedaKiyoko SatoNobuo SakiyamaHirokuni YanoTakuya Hayashi
    • G06F15/16
    • G06F9/4862
    • Process migration method includes copying first process context indicative of first processing, transmitting process context to second computer, causing first computer to start generation of first execution record, causing second computer to receive process context, determining, from first execution record, whether first processing should be migrated, if it is determined that first processing should postpone being migrated, finishing generation of first execution record, starting generation of second execution record, transmitting first execution record to second computer, reproducing process context, and determining, from second execution record, whether first processing should be migrated, after reproducing of process context is finished in the second computer.
    • 过程迁移方法包括复制指示第一处理的第一处理上下文,将处理上下文传送给第二计算机,使第一计算机开始生成第一执行记录,使第二计算机接收进程上下文,从第一执行记录确定第一处理是否应当 如果确定第一处理被推迟被迁移,则完成第一执行记录的生成,开始生成第二执行记录,将第一执行记录发送到第二计算机,再现处理环境,以及从第二执行记录确定是否 在第二台计算机中完成处理上下文的再现之后,应该首先进行处理。