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1. 发明授权

US5472564A Method of dry etching with hydrogen bromide or bromide 失效
标题翻译：用溴化氢或溴化物干蚀刻的方法
公开(公告)号：US5472564A
公开(公告)日：1995-12-05
申请号：US104546
申请日：1993-08-11
申请人： Moritaka Nakamura , Takashi Kurimoto , Katsuhiko Iizuka
发明人： Moritaka Nakamura , Takashi Kurimoto , Katsuhiko Iizuka
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3213 , H01L29/423 , H01L21/306
CPC分类号： H01L21/31138 , H01L21/28114 , H01L21/32137 , H01L29/42376
摘要： Plasma etching with hydrogen bromide or bromine as an etching gas allows a precise control in attaining vertical etching or taper etching with a desired taper angle by controlling the temperature of a mass to be etched, which mass is usually a semiconductor wafer.
摘要翻译：使用溴化氢或溴作为蚀刻气体的等离子体蚀刻允许通过控制要蚀刻的质量的温度来获得具有期望的锥角的垂直蚀刻或锥形蚀刻的精确控制，该质量通常是半导体晶片。

2. 发明授权

US5316616A Dry etching with hydrogen bromide or bromine 失效
标题翻译：用溴化氢或溴进行干蚀刻
公开(公告)号：US5316616A
公开(公告)日：1994-05-31
申请号：US68615
申请日：1993-05-27
申请人： Moritaka Nakamura , Takashi Kurimoto , Katsuhiko Iizuka
发明人： Moritaka Nakamura , Takashi Kurimoto , Katsuhiko Iizuka
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3213 , H01L29/423 , H01L21/306
CPC分类号： H01L21/31138 , H01L21/28114 , H01L21/32137 , H01L29/42376
摘要： Plasma etching with hydrogen bromide or bromine as an etching gas allows a precise control of attaining vertical etching or taper etching with a desired taper angle by controlling a temperature of a mass to be etched, which mass is a phosphorus-doped n-type polycrystalline silicon, phosphorus-doped single crystalline or phosphorus-doped silicides semiconductor wafer.
摘要翻译：使用溴化氢或溴作为蚀刻气体的等离子体蚀刻允许通过控制要蚀刻的质量的温度来精确控制获得垂直蚀刻或具有期望的锥角的锥形蚀刻，该质量是磷掺杂的n型多晶硅磷掺杂单晶或磷掺杂硅化物半导体晶片。

3. 发明申请

US20050136629A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050136629A1
公开(公告)日：2005-06-23
申请号：US10974970
申请日：2004-10-28
申请人： Katsuhiko Iizuka , Kazuo Okada , Tomonori Mori , Hiroyuki Dobashi , Hiroyuki Suzuki , Takayoshi Honda , Toshimitsu Taniguchi
发明人： Katsuhiko Iizuka , Kazuo Okada , Tomonori Mori , Hiroyuki Dobashi , Hiroyuki Suzuki , Takayoshi Honda , Toshimitsu Taniguchi
IPC分类号： H01L21/02 , H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/665 , H01L29/7833
摘要： An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.
摘要翻译：形成LDD结构和硅化物层，而不会减小硅衬底的厚度或碳污染。在栅电极的侧壁上形成间隔物，在两个工艺步骤中进行，即干蚀刻和湿蚀刻。此外，通过湿蚀刻除去用作注入大量杂质的缓冲膜的氮化硅膜。结果，可以防止硅衬底的厚度减少和碳污染。此外，由于湿蚀刻可用的高选择比，可以抑制高和低杂质浓度区域和硅化物形成区域在晶片上的位置的深度变化。

4. 发明授权

US5487811A Process for preparation of semiconductor device 失效
标题翻译：半导体器件的制备方法
公开(公告)号：US5487811A
公开(公告)日：1996-01-30
申请号：US748157
申请日：1991-08-21
申请人： Katsuhiko Iizuka
发明人： Katsuhiko Iizuka
IPC分类号： H01L21/302 , H01L21/28 , H01L21/3065 , H01L21/3213 , H01L29/423 , H01L29/43 , H01L29/49 , H01L21/00
CPC分类号： H01L21/32137
摘要： A process for the preparation of a semiconductor device, includes the steps of, (a) foxing a mask including an organic film on a laminated film consisting of a metal silicide layer and a non-single crystalline silicon layer formed over a substrate on which an oxide layer is formed, (b) etching the laminated film under a plasma atmosphere of a mixed gas including a chlorine gas and an oxygen gas by heating the substrate to a temperature of 60.degree. C. or more to fabricate the laminated film into an almost vertical pattern in section, and (c) removing the mask from the laminated film. In this process, the laminated film consisting of a metal silicide layer on which a resist mask is formed, and a polycrystalline silicon layer formed over a substrate, can be given vertical patterning profile edge, and the uniformity of the etching rate in the substrate is enhanced. Further, as a deposition gas is not used in the present process, the occurrence of loose particles is restrained.
摘要翻译：一种制备半导体器件的方法，包括以下步骤：（a）在由金属硅化物层和非单晶硅层组成的层压膜上氧化包含有机膜的掩模，所述金属硅化物层和非单晶硅层在其上形成形成氧化物层，（b）在包含氯气和氧气的混合气体的等离子体气氛下，通过将基板加热到60℃以上的温度来对层叠膜进行蚀刻，制成层叠膜剖面中的垂直图案，（c）从层压膜上除去掩模。在该工序中，由形成有抗蚀剂掩模的金属硅化物层和在基板上形成的多晶硅层构成的层叠膜可以具有垂直的图案形状边缘，并且基板中的蚀刻速度的均匀性为增强。此外，由于在本方法中不使用沉积气体，所以抑制松散颗粒的发生。

5. 发明授权

US07022575B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07022575B2
公开(公告)日：2006-04-04
申请号：US10974970
申请日：2004-10-28
申请人： Katsuhiko Iizuka , Kazuo Okada , Tomonori Mori , Hiroyuki Dobashi , Hiroyuki Suzuki , Takayoshi Honda , Toshimitsu Taniguchi
发明人： Katsuhiko Iizuka , Kazuo Okada , Tomonori Mori , Hiroyuki Dobashi , Hiroyuki Suzuki , Takayoshi Honda , Toshimitsu Taniguchi
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/28 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/665 , H01L29/7833
摘要： An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.
摘要翻译：形成LDD结构和硅化物层，而不会减小硅衬底的厚度或碳污染。在栅电极的侧壁上形成间隔物，在两个工艺步骤中进行，即干蚀刻和湿蚀刻。此外，通过湿蚀刻除去用作注入大量杂质的缓冲膜的氮化硅膜。结果，可以防止硅衬底的厚度减少和碳污染。此外，由于湿蚀刻可用的高选择比，可以抑制具有晶片上位置的高和低杂质浓度区域和硅化物形成区域的深度变化。

6. 发明授权

US06987062B2 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06987062B2
公开(公告)日：2006-01-17
申请号：US10974971
申请日：2004-10-28
申请人： Katsuhiko Iizuka , Kazuo Okada
发明人： Katsuhiko Iizuka , Kazuo Okada
IPC分类号： H01L21/44 , H01L21/336 , H01L21/302
CPC分类号： H01L29/458 , H01L21/31111 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66772
摘要： This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a gate insulation film, an insulation film made of the same material as the gate insulation film is formed on the gate electrode. A first insulation film made of a material different from the material of the gate insulation film and the insulation film on the gate electrode and a second insulation film made of the same material as the material of the gate insulation film and the insulation film on the gate electrode are formed over the silicon substrate. Spacers made of the second insulation film are formed by dry-etching. Then the LDD structure and openings for forming the silicide layers are formed using wet-etching. As a result, the transistor having the LDD structure and the silicide layers formed by the salicide technology is manufactured without causing the reduction in thickness of the silicon substrate or the carbon contamination.
摘要翻译：本发明提供了一种制造方法，其不会导致在形成具有LDD限制的晶体管和由硅化物技术形成的硅化物层的硅衬底的厚度减少或碳污染。在栅极电极通过栅极绝缘膜形成在硅衬底上之后，在栅电极上形成由与栅极绝缘膜相同的材料制成的绝缘膜。由与栅极绝缘膜的材料和栅电极上的绝缘膜不同的材料制成的第一绝缘膜和由与栅极绝缘膜和栅极上的绝缘膜相同的材料制成的第二绝缘膜电极形成在硅衬底上。通过干法蚀刻形成由第二绝缘膜制成的间隔物。然后，使用湿蚀刻形成用于形成硅化物层的LDD结构和开口。结果，制造具有LDD结构的晶体管和由硅化物技术形成的硅化物层，而不会导致硅衬底的厚度减小或碳污染。

7. 发明申请

US20050136603A1 Manufacturing method of semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US20050136603A1
公开(公告)日：2005-06-23
申请号：US10974971
申请日：2004-10-28
申请人： Katsuhiko Iizuka , Kazuo Okada
发明人： Katsuhiko Iizuka , Kazuo Okada
IPC分类号： H01L21/311 , H01L21/336 , H01L29/45
CPC分类号： H01L29/458 , H01L21/31111 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66772
摘要： This invention offers a manufacturing method which does not cause a reduction in thickness of a silicon substrate or a carbon contamination in forming a transistor having an LDD stricture and silicide layers formed by a salicide technology. After a gate electrode is formed on the silicon substrate through a gate insulation film, an insulation film made of the same material as the gate insulation film is formed on the gate electrode. A first insulation film made of a material different from the material of the gate insulation film and the insulation film on the gate electrode and a second insulation film made of the same material as the material of the gate insulation film and the insulation film on the gate electrode are formed over the silicon substrate. Spacers made of the second insulation film are formed by dry-etching. Then the LDD structure and openings for forming the silicide layers are formed using wet-etching. As a result, the transistor having the LDD structure and the silicide layers formed by the salicide technology is manufactured without causing the reduction in thickness of the silicon substrate or the carbon contamination.
摘要翻译：本发明提供了一种制造方法，其不会导致在形成具有LDD限制的晶体管和由硅化物技术形成的硅化物层的硅衬底的厚度减少或碳污染。在栅极电极通过栅极绝缘膜形成在硅衬底上之后，在栅电极上形成由与栅极绝缘膜相同的材料制成的绝缘膜。由与栅极绝缘膜的材料和栅电极上的绝缘膜不同的材料制成的第一绝缘膜和由与栅极绝缘膜和栅极上的绝缘膜相同的材料制成的第二绝缘膜电极形成在硅衬底上。通过干法蚀刻形成由第二绝缘膜制成的间隔物。然后，使用湿蚀刻形成用于形成硅化物层的LDD结构和开口。结果，制造具有LDD结构的晶体管和由硅化物技术形成的硅化物层，而不会导致硅衬底的厚度减小或碳污染。

8. 发明授权

US5756401A Process for the etching of polycide film 失效
标题翻译：多晶硅薄膜蚀刻工艺
公开(公告)号：US5756401A
公开(公告)日：1998-05-26
申请号：US27634
申请日：1993-03-08
申请人： Katsuhiko Iizuka
发明人： Katsuhiko Iizuka
IPC分类号： H01L21/3213 , H01L21/30
CPC分类号： H01L21/32137
摘要： There is provided a process of dry etching of a double-layer film composed of a polycrystal silicon film and a metal silicide film formed on a base substance with an etching-proof film composed of an inorganic compound as a mask in a state that reaction gas loaded with at least any one of HBr gas, Br.sub.2 gas and BBr.sub.3 gas is activated by plasma discharge, and the temperature of the base substance is maintained at 60.degree. C. or higher. With this, it is possible to aim at improvement of dimensional controllability and selectivity of etching without using flon gas, and further to arrange so that the configuration after etching of an object to be etched does not depend on an area ratio on a wafer of the area of a region where an etching-proof film is formed to the exposed area of the object to be etched.
摘要翻译：提供了在反应气体的状态下，将由多晶硅膜和形成在基体上的金属硅化物膜构成的双层膜与由无机化合物组成的防蚀膜作为掩模进行干法蚀刻的工艺装有HBr气体，Br2气体和BBr3气体中的至少一种的气体通过等离子体放电而被激活，并且基础物质的温度保持在60℃以上。由此，可以在不使用氟里昂气体的前提下，提高尺寸可控性和蚀刻选择性，并且进一步设置为使得待蚀刻对象的蚀刻后的结构不依赖于晶片上的面积比在被蚀刻对象的曝光区域形成防蚀膜的区域的面积。

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